Paper ID: 2212.03515

FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training

Keren Liu, Erik Börjeson, Christian Häger, Per Larsson-Edefors

We design and implement an adaptive machine learning equalizer that alternates multiple linear and nonlinear computational layers on an FPGA. On-chip training via gradient backpropagation is shown to allow for real-time adaptation to time-varying channel impairments.

Submitted: Dec 7, 2022