Field Programmable Gate Array

Field-Programmable Gate Arrays (FPGAs) are reconfigurable hardware devices increasingly used to accelerate machine learning (ML) inference, particularly for resource-constrained applications like edge computing. Current research focuses on optimizing various ML model architectures, including transformers, convolutional neural networks (CNNs), and recurrent neural networks (RNNs), for efficient deployment on FPGAs, often employing techniques like quantization and model compression to reduce resource usage and latency. This work is significant because it enables the deployment of powerful ML models on low-power, embedded devices, impacting diverse fields from real-time image processing in robotics and scientific instrumentation to high-throughput data analysis in high-energy physics.

Papers

July 2, 2024

Fast, Scalable, Energy-Efficient Non-element-wise Matrix Multiplication on FPGA
Xuqi Zhu, Huaizhi Zhang, JunKyu Lee, Jiacheng Zhu, Chandrajit Pal, Sangeet Saha, Klaus D. McDonald-Maier, Xiaojun Zhai
Field Programmable Gate Array Matrix Multiplication

July 1, 2024

Exploring FPGA designs for MX and beyond
Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
Field Programmable Gate Array Pytorch Model Low Precision Multi FPGA

June 23, 2024

Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA
Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk
Field Programmable Gate Array Uncertainty Prediction Dropout Regularization Inference Based Adaptive Dropout Dropout Based

June 21, 2024

PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers
Mohammad Erfan Sadeghi, Arash Fayyazi, Seyedarmin Azizi, Massoud Pedram
Vision Transformer Field Programmable Gate Array Layer Normalization Divide and Conquer Approximation Power Non Linearity FPGA Resource

June 20, 2024

Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA
Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan
Bayesian Neural Network Field Programmable Gate Array Multi Exit Bayes Net Dropout Based

June 17, 2024

RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications
Zhuoheng Ran, Muhammad A. A. Abdelgawad, Zekai Zhang, Ray C. C. Cheung, Hong Yan
Field Programmable Gate Array Generated Content Reconfigurable Intelligent Copyright Traceability AI Hardware

June 9, 2024

Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers
Vincenzo Liguori
Field Programmable Gate Array Long Sequence Exceptional Point Lazy Search Discrete Logarithm Directed Accumulator

June 7, 2024

PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs
Binglei Lou, Richard Rademacher, David Boland, Philip H.W. Leong
Deep Neural Network Field Programmable Gate Array Lookup Table Long Input

June 6, 2024

Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC
Julien Posso, Guy Bois, Yvon Savaria
Neural Network Field Programmable Gate Array Multi FPGA FPGA Resource Spacecraft Pose Estimation

May 27, 2024

SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs
Zhenyu Bai, Pranav Dangi, Huize Li, Tulika Mitra
Potential Scalability Field Programmable Gate Array Sparse Attention Dataflow Architecture Attention Based Transformer Police Public Interaction Self Attention Computation Window Selection

May 8, 2024

Controlling Chaos Using Edge Computing Hardware
Robert M. Kent, Wendson A. S. Barbosa, Daniel J. Gauthier
Field Programmable Gate Array Reservoir Computing Quantum State Chaotic System Nonlinear Control Chaos Theory

May 3, 2024

Fast Algorithms for Spiking Neural Network Simulation with FPGAs
Björn A. Lindqvist, Artur Podobas
Spiking Neural Network Field Programmable Gate Array Hardware Accelerator Fast Algorithm Neural Microcircuit

May 2, 2024

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
Paola Vitolo, George Psaltakis, Michael Tomlinson, Gian Domenico Licciardo, Andreas G. Andreou
Natural Language ChatGPT Generated Conversation Spiking Neural Network Field Programmable Gate Array Recurrent Network Hardware Description Language Functional Verilog Description Core Neuromorphic

April 29, 2024

HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis
Andy He, Darren Key, Mason Bulling, Andrew Chang, Skyler Shapiro, Everett Lee
Scientific Inference Field Programmable Gate Array Hardware Accelerator Multi FPGA FPGA Accelerator Fine Tuned Llama

April 26, 2024

Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
Julia Gonski, Aseem Gupta, Haoyi Jia, Hyunjoon Kim, Lorenzo Rota, Larry Ruckman, Angelo Dragone, Ryan Herbst
Machine Learning Field Programmable Gate Array Multi FPGA Complementary Metal Oxide Semiconductor FPGA Implementation Particle Detector Readout Head

April 22, 2024

CNN-Based Equalization for Communications: Achieving Gigabit Throughput with a Flexible FPGA Hardware Architecture
Jonas Ney, Christoph Füllner, Vincent Lauinger, Laurent Schmalen, Sebastian Randel, Norbert Wehn
Field Programmable Gate Array Timely Communication Worst Case User Throughput Optical Network Parametric Equalizer Neural Network Based Equalizer

April 19, 2024

Investigating Resource-efficient Neutron/Gamma Classification ML Models Targeting eFPGAs
Jyothisraj Johnson, Billy Boxer, Tarun Prakash, Carl Grace, Peter Sorensen, Mani Tripathi
Machine Learning Model Field Programmable Gate Array Gamma Belief Network Inelastic Neutron

April 16, 2024

From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs
Vincenzo Liguori
CNN Model Field Programmable Gate Array Data Compression Hardware Implementation LLaMA Model Lossless Performance Computational System Numeral System

April 13, 2024

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach
Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, Rainer Buchty, Mladen Berekovic, Saleh Mulhem
Field Programmable Gate Array Intrusion Detection System Systematic Approach Edge Application

April 11, 2024

FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning
Shang Wang, Deepak Ranganatha Sastry Mamillapalli, Tianpei Yang, Matthew E. Taylor
Deep Reinforcement Learning Field Programmable Gate Array Logic Design Stable Placement

Field Programmable Gate Array

Papers

Fast, Scalable, Energy-Efficient Non-element-wise Matrix Multiplication on FPGA

Exploring FPGA designs for MX and beyond

Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA

PEANO-ViT: Power-Efficient Approximations of Non-Linearities in Vision Transformers

Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA

RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications

Procrastination Is All You Need: Exponent Indexed Accumulators for Floating Point, Posits and Logarithmic Numbers

PolyLUT-Add: FPGA-based LUT Inference with Wide Inputs

Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC

SWAT: Scalable and Efficient Window Attention-based Transformers Acceleration on FPGAs

Controlling Chaos Using Edge Computing Hardware

Fast Algorithms for Spiking Neural Network Simulation with FPGAs

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis

Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout

CNN-Based Equalization for Communications: Achieving Gigabit Throughput with a Flexible FPGA Hardware Architecture

Investigating Resource-efficient Neutron/Gamma Classification ML Models Targeting eFPGAs

From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach

FPGA Divide-and-Conquer Placement using Deep Reinforcement Learning