FPGA Accelerator

FPGA accelerators are hardware devices designed to significantly speed up the execution of computationally intensive algorithms, particularly in machine learning. Current research focuses on optimizing these accelerators for various neural network architectures, including transformers (like those used in large language models), convolutional neural networks, and spiking neural networks, often employing techniques like pipelining, systolic arrays, and mixed-scheme quantization to maximize throughput and energy efficiency. This work is crucial for deploying advanced AI models on resource-constrained devices like edge computers and embedded systems, enabling faster and more power-efficient applications in diverse fields such as computer vision, natural language processing, and robotics.

Papers

September 21, 2024

August 5, 2024

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part II: Architecture and Hardware Implementation
Cristian Sestito, Shady Agwa, Themis Prodromakis
Convolutional Neural Network Field Programmable Gate Array Architecture Design FPGA Accelerator Hardware Implementation Systolic Array

August 1, 2024

Designing Efficient LLM Accelerators for Edge Devices
Jude Haris, Rappy Saha, Wenhao Hu, José Cano
Edge Device Multi FPGA FPGA Accelerator Lightweight LLM Hardware Constraint

July 25, 2024

HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline
Qingyu Guo, Jiayong Wan, Songqiang Xu, Meng Li, Yuan Wang
Vision Transformer FPGA Accelerator Software Evolution

July 7, 2024

Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network
Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk
Bayesian Neural Network Magnetic Resonance FPGA Accelerator

July 4, 2024

Low-latency machine learning FPGA accelerator for multi-qubit-state discrimination
Pradeep Kumar Gautam, Shantharam Kalipatnapu, Shankaranarayanan H, Ujjawal Singhal, Benjamin Lienhard, Vibhor Singh, Chetan Singh Thakur
Quantum Computing Low Latency Multiple Physical Qubits FPGA Accelerator Readout Model

May 2, 2024

Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design
Jian Meng, Yuan Liao, Anupreetham Anupreetham, Ahmed Hasssan, Shixing Yu, Han-sok Suh, Xiaofeng Hu, Jae-sun Seo
End to End Model Compression Easy to Use Toolkit Neural Network Compression Chip Design FPGA Accelerator Algorithm Hardware Co Design

April 29, 2024

HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis
Andy He, Darren Key, Mason Bulling, Andrew Chang, Skyler Shapiro, Everett Lee
Scientific Inference Field Programmable Gate Array Hardware Accelerator Multi FPGA FPGA Accelerator Fine Tuned Llama

April 4, 2024

SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA
Dario Padovano, Alessio Carpegna, Alessandro Savino, Stefano Di Carlo
Neural Network Field Programmable Gate Array Hardware Accelerator Design Space Exploration FPGA Accelerator

March 29, 2024

An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT
Haikuo Shao, Huihong Shi, Wendong Mao, Zhongfeng Wang
Vision Transformer Hardware Accelerator Memory Efficient Hybrid CNN Transformer FPGA Accelerator Efficient Hardware

January 22, 2024

BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge
Yuhao Ji, Chao Fang, Zhongfeng Wang
Extreme Edge Matrix Multiplication FPGA Accelerator Edge Transformer Transformer Accelerator Binary Vision Transformer

December 23, 2023

An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm
Kazuki Sunaga, Keisuke Sugiura, Hiroki Matsutani
Graph Drawing Field Programmable Gate Array Graph Structure Sequential Learning FPGA Accelerator Node2vec Application

September 28, 2023

FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator
Jindong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng
Spiking Neural Network Spike Based FPGA Accelerator Hardware Error Octopus V2

September 4, 2023

SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices
Alexander Montgomerie-Corcoran, Petros Toupas, Zhewen Yu, Christos-Savvas Bouganis
YOLO Model FPGA Accelerator Edge Platform Streaming Capable High Performance Architecture

July 5, 2023

Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines
Yuxin Yang, Xiaoming Chen, Yinhe Han
Rigid Body Robot Dynamic Rigid Robot FPGA Accelerator Stage Pipeline

June 30, 2023

An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning
Keisuke Sugiura, Hiroki Matsutani
Point Cloud Path Planning FPGA Accelerator Neural Motion

April 13, 2023

DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference
Hanqiu Chen, Cong Hao
FPGA Accelerator GNN Acceleration

January 5, 2023

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization
Jindong Li, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng
Neural Network State of the Art Field Programmable Gate Array FPGA Accelerator Memory Optimization

August 10, 2022

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization
Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang
Vision Transformer FPGA Accelerator

FPGA Accelerator

Papers

FAMOUS: Flexible Accelerator for the Attention Mechanism of Transformer on UltraScale+ FPGAs

ProTEA: Programmable Transformer Encoder Acceleration on FPGA

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part II: Architecture and Hardware Implementation

Designing Efficient LLM Accelerators for Edge Devices

HG-PIPE: Vision Transformer Acceleration with Hybrid-Grained Pipeline

Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network

Low-latency machine learning FPGA accelerator for multi-qubit-state discrimination

Torch2Chip: An End-to-end Customizable Deep Neural Network Compression and Deployment Toolkit for Prototype Hardware Accelerator Design

HLSTransform: Energy-Efficient Llama 2 Inference on FPGAs Via High Level Synthesis

SpikeExplorer: hardware-oriented Design Space Exploration for Spiking Neural Networks on FPGA

An FPGA-Based Reconfigurable Accelerator for Convolution-Transformer Hybrid EfficientViT

BETA: Binarized Energy-Efficient Transformer Accelerator at the Edge

An FPGA-Based Accelerator for Graph Embedding using Sequential Training Algorithm

FireFly v2: Advancing Hardware Support for High-Performance Spiking Neural Network with a Spatiotemporal FPGA Accelerator

SATAY: A Streaming Architecture Toolflow for Accelerating YOLO Models on FPGA Devices

Dadu-RBD: Robot Rigid Body Dynamics Accelerator with Multifunctional Pipelines

An Integrated FPGA Accelerator for Deep Learning-based 2D/3D Path Planning

DGNN-Booster: A Generic FPGA Accelerator Framework For Dynamic Graph Neural Network Inference

FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Networks with Efficient DSP and Memory Optimization

Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization