Functional Verilog Description

Functional Verilog description focuses on automatically generating and debugging Verilog code, a hardware description language crucial for designing integrated circuits. Current research heavily utilizes large language models (LLMs), often fine-tuned on specialized Verilog datasets and sometimes integrated with graph-based planning or other AI agents, to improve the syntactic and functional correctness of generated code, as well as to aid in bug localization and test generation. This automation holds significant promise for accelerating and improving the accuracy of hardware design, reducing development time and costs, and potentially making hardware design more accessible.

Papers

September 23, 2024

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
Large Language Model Location Information Verilog Code Generation Functional Verilog Description BUG Localization Verilog Textbook

August 15, 2024

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung Ho, Haoxing Ren, Brucek Khailany
Abstract Syntax Tree Verilog Code Generation Waveform Model Graph Based Planning Functional Verilog Description

July 21, 2024

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs
Mingzhe Gao, Jieru Zhao, Zhe Lin, Wenchao Ding, Xiaofeng Hou, Yu Feng, Chao Li, Minyi Guo
Large Language Model Code Generation LLM Benchmark Verilog Code Generation Functional Verilog Description

July 15, 2024

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization
Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Ziyuan Nan, Tianyun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
Large Language Model Hardware Description Language Verilog Code Generation Single Document Summarization Functional Verilog Description Design Automation

July 2, 2024

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation
Yongan Zhang, Zhongzhi Yu, Yonggan Fu, Cheng Wan, Yingyan Celine Lin
Data Set Functional Verilog Description Verilog Textbook

June 3, 2024

VerilogReader: LLM-Aided Hardware Test Generation
Ruiyang Ma, Yuxin Yang, Ziqian Liu, Jiaxi Zhang, Min Li, Junhua Huang, Guojie Luo
Test Generation Functional Verilog Description Coverage Directed Test Benchmark Circuit

May 2, 2024

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
Paola Vitolo, George Psaltakis, Michael Tomlinson, Gian Domenico Licciardo, Andreas G. Andreou
Natural Language ChatGPT Generated Conversation Spiking Neural Network Field Programmable Gate Array Recurrent Network Hardware Description Language Functional Verilog Description Core Neuromorphic

April 23, 2024

Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce
Large Language Model Level Test Hardware Design Chip Design Hardware Description Language Functional Verilog Description

April 11, 2024

A Multi-Expert Large Language Model Architecture for Verilog Code Generation
Bardia Nadimi, Hao Zheng
Verilog Code Generation Functional Verilog Description LLM RBMT Expert Language Model Design Knowledge

February 3, 2024

BetterV: Controlled Verilog Generation with Discriminative Guidance
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
Electronic Design Automation Hardware Description Language Verilog Code Generation Functional Verilog Description Discriminator Guidance

January 25, 2024

Designing Silicon Brains using LLM: Leveraging ChatGPT for Automated Description of a Spiking Neuron Array
Michael Tomlinson, Joe Li, Andreas Andreou
Large Language Model Medical LLM ChatGPT Generated Conversation Code Generation Natural Language Description Spiking Neuron Based Design Functional Verilog Description

April 26, 2023

A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Enrique Dehaerne, Bappaditya Dey, Sandip Halder, Stefan De Gendt
Product Design Deep Learning Framework Hardware Description Language Verilog Code Generation Functional Verilog Description Verilog Textbook

December 13, 2022

Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg
Verilog Code Generation Functional Verilog Description Verilog Textbook

Functional Verilog Description

Papers

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool

AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization

MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation

VerilogReader: LLM-Aided Hardware Test Generation

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

Evaluating LLMs for Hardware Design and Test

A Multi-Expert Large Language Model Architecture for Verilog Code Generation

BetterV: Controlled Verilog Generation with Discriminative Guidance

Designing Silicon Brains using LLM: Leveraging ChatGPT for Automated Description of a Spiking Neuron Array

A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation

Benchmarking Large Language Models for Automated Verilog RTL Code Generation