Hardware Description Language

Hardware Description Languages (HDLs), such as Verilog and VHDL, are used to describe the structure and behavior of digital circuits. Current research focuses on leveraging large language models (LLMs), often fine-tuned on large corpora of HDL code, to automate tasks like code generation, verification, and even complete chip design. This involves exploring various LLM architectures and prompting techniques to improve code quality, address issues like "hallucination" (generating incorrect code), and handle non-textual representations common in circuit design. The ultimate goal is to accelerate and improve the efficiency and reliability of the electronic design automation (EDA) process, leading to faster and more cost-effective chip development.

Papers

October 30, 2024

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang, Didier Chetelat, Dimitrios Tsaras, Yingxue Zhang, Hui-Ling Zhen, Jianye Hao, Mingxuan Yuan
Graph Drawing Quality Estimation Logic Synthesis Hardware Description Language Biological Circuit Digital Circuit Apprenticeship Learning Verilog Textbook

September 19, 2024

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair
Mingjie Liu, Yun-Da Tsai, Wenfei Zhou, Haoxing Ren
Code Generation Synthetic Data Generation Contextual Representation Fine Tuned LLM Hardware Description Language Adaptive Machine

August 20, 2024

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks
Nathaniel Pinckney, Christopher Batten, Mingjie Liu, Haoxing Ren, Brucek Khailany
Large Language Model Context Learning Hardware Description Language Register Transfer Level

July 25, 2024

HDL-GPT: High-Quality HDL is All You Need
Bhuvnesh Kumar, Saurav Nanda, Ganapathy Parthasarathy, Pawan Patil, Austin Tsai, Parivesh Choudhary
Code Generation Hardware Description Language Large Code Model VHDL Code

July 23, 2024

Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design
Andre Nakkab, Sai Qian Zhang, Ramesh Karri, Siddharth Garg
Hardware Description Language Tuned Llama Model Hierarchical Prompting

July 15, 2024

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization
Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Ziyuan Nan, Tianyun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
Large Language Model Hardware Description Language Verilog Code Generation Single Document Summarization Functional Verilog Description Design Automation

July 4, 2024

Classification-Based Automatic HDL Code Generation Using LLMs
Wenhao Sun, Bing Li, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Ulf Schlichtmann
Large Language Model Code Generation Electronic Design Automation Hardware Description Language Digital Circuit

June 13, 2024

Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis
Zongyue Qin, Yunsheng Bai, Atefeh Sohrabizadeh, Zijian Ding, Ziniu Hu, Yizhou Sun, Jason Cong
Design Space Exploration High Level Synthesis Electronic Design Automation Hardware Description Language Domain Specific Accelerator Program Representation

May 11, 2024

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
Zeng Wang, Lilas Alrahis, Likhitha Mankali, Johann Knechtel, Ozgur Sinanoglu
Medical LLM Future Reasoning Building Trust Chip Design Electronic Design Automation Hardware Description Language Circuit Model Unveiling Vulnerability

May 2, 2024

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT
Paola Vitolo, George Psaltakis, Michael Tomlinson, Gian Domenico Licciardo, Andreas G. Andreou
Natural Language ChatGPT Generated Conversation Spiking Neural Network Field Programmable Gate Array Recurrent Network Hardware Description Language Functional Verilog Description Core Neuromorphic

April 25, 2024

Digital ASIC Design with Ongoing LLMs: Strategies and Prospects
Maoyang Xiang, Emil Goh, T. Hui Teo
General Strategy Visionary ProSpect Hardware Description Language Integrated Circuit Design AI Hardware ASIC Design

April 23, 2024

Evaluating LLMs for Hardware Design and Test
Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce
Large Language Model Level Test Hardware Design Chip Design Hardware Description Language Functional Verilog Description

March 25, 2024

All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification
Deepak Narayan Gadde, Aman Kumar, Thomas Nalapat, Evgenii Rezunov, Fabio Cappellini
Camera Lens Synthetic to Real Cognitive Intelligence Formal Verification Hardware Design GenAI Integration Hardware Description Language

March 17, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, yinhe han, Huawei Li, Xiaowei Li
Large Language Model Raw Data Chip Design Electronic Design Automation Hardware Description Language Verilog Code Generation Iterative Design

February 3, 2024

BetterV: Controlled Verilog Generation with Discriminative Guidance
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
Electronic Design Automation Hardware Description Language Verilog Code Generation Functional Verilog Description Discriminator Guidance

January 30, 2024

Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators
Mika Markus Müller, Alexander Richard Manfred Borst, Konstantin Lübeck, Alexander Louis-Ferdinand Jung, Oliver Bringmann
Hardware Accelerator Hardware Design Hardware Description Language Multi Accelerator

December 28, 2023

LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
Ruizhe Zhong, Xingbo Du, Shixiong Kai, Zhentao Tang, Siyuan Xu, Hui-Ling Zhen, Jianye Hao, Qiang Xu, Mingxuan Yuan, Junchi Yan
Much Progress Chip Design Electronic Design Automation Logic Synthesis Hardware Description Language

August 15, 2023

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR
Jianyi Cheng, Samuel Coward, Lorenzo Chelini, Rafael Barbalho, Theo Drane
High Level Synthesis Modern Compiler Hardware Description Language Optimization Performance E Graph

May 22, 2023

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design
Jason Blocklove, Siddharth Garg, Ramesh Karri, Hammond Pearce
Technical Challenge Emerging Opportunity Hardware Design Hardware Description Language Design Generation Hardware Constraint

May 18, 2023

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation
Yunsheng Bai, Atefeh Sohrabizadeh, Zongyue Qin, Ziniu Hu, Yizhou Sun, Jason Cong
Field Programmable Gate Array Past Present Temporal Program High Level Synthesis Electronic Design Automation Cross Modal Representation Learning Hardware Description Language Domain Specific Accelerator

Hardware Description Language

Papers

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation

CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair

Revisiting VerilogEval: Newer LLMs, In-Context Learning, and Specification-to-RTL Tasks

HDL-GPT: High-Quality HDL is All You Need

Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization

Classification-Based Automatic HDL Code Generation Using LLMs

Cross-Modality Program Representation Learning for Electronic Design Automation with High-Level Synthesis

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust

Natural Language to Verilog: Design of a Recurrent Spiking Neural Network using Large Language Models and ChatGPT

Digital ASIC Design with Ongoing LLMs: Strategies and Prospects

Evaluating LLMs for Hardware Design and Test

All Artificial, Less Intelligence: GenAI through the Lens of Formal Verification

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

BetterV: Controlled Verilog Generation with Discriminative Guidance

Using the Abstract Computer Architecture Description Language to Model AI Hardware Accelerators

LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation

SEER: Super-Optimization Explorer for HLS using E-graph Rewriting with MLIR

Chip-Chat: Challenges and Opportunities in Conversational Hardware Design

ProgSG: Cross-Modality Representation Learning for Programs in Electronic Design Automation