HDL Code

Hardware Description Languages (HDLs) are crucial for designing integrated circuits, but their complex syntax makes debugging challenging. Current research focuses on leveraging large language models (LLMs) to automate HDL debugging and even generate HDL code directly from natural language specifications, addressing the need for more efficient and accurate ASIC design. This involves fine-tuning LLMs on specialized HDL datasets and developing frameworks that combine LLMs with search engines to improve code generation and debugging accuracy, ultimately aiming to streamline the complex process of chip design.

Papers

March 18, 2024

HDLdebugger: Streamlining HDL debugging with Large Language Models
Xufeng Yao, Haoyang Li, Tsz Ho Chan, Wenyi Xiao, Mingxuan Yuan, Yu Huang, Lei Chen, Bei Yu
HDL Code

March 11, 2024

From English to ASIC: Hardware Implementation with Large Language Model
Emil Goh, Maoyang Xiang, I-Chyn Wey, T. Hui Teo
Large Language Model Circuit Design Hardware Implementation Digital Circuit ASIC Design HDL Code

HDL Code

Papers

HDLdebugger: Streamlining HDL debugging with Large Language Models

From English to ASIC: Hardware Implementation with Large Language Model