High Level Synthesis

High-level synthesis (HLS) automates the translation of high-level code (like C++) into hardware designs, accelerating the development of hardware accelerators. Current research emphasizes using machine learning, particularly graph neural networks (GNNs) and large language models (LLMs), to optimize the HLS process, focusing on efficient design space exploration and accurate performance prediction before full synthesis. This improves the efficiency and productivity of hardware design, impacting fields like AI acceleration and embedded systems by enabling faster development cycles and potentially higher-performing hardware.