Logic Synthesis

Logic synthesis optimizes the design of digital circuits by transforming high-level descriptions into efficient netlists of logic gates, aiming to minimize metrics like size, delay, and power consumption. Current research heavily utilizes machine learning, employing graph neural networks (GNNs), transformers, and reinforcement learning (RL) to predict circuit quality-of-results (QoR) and automate the selection of synthesis algorithms, often incorporating techniques like multi-task learning and Bayesian optimization for improved efficiency and generalization. These advancements promise significant improvements in the speed and quality of chip design, impacting the efficiency and scalability of the entire electronic design automation (EDA) workflow.

Papers

November 14, 2024

An Adaptive Open-Source Dataset Generation Framework for Machine Learning Tasks in Logic Synthesis
Liwei Ni, Rui Wang, Miao Liu, Xingyu Meng, Xiaoze Lin, Junfeng Liu, Guojie Luo, Zhufei Chu, Weikang Qian, Xiaoyan Yang, Biwei Xie, Xingquan Li, Huawei Li
New Machine Dataset Generation Logic Synthesis Learning Task Adaptive Machine

October 30, 2024

The Graph's Apprentice: Teaching an LLM Low Level Knowledge for Circuit Quality Estimation
Reza Moravej, Saurabh Bodhe, Zhanguang Zhang, Didier Chetelat, Dimitrios Tsaras, Yingxue Zhang, Hui-Ling Zhen, Jianye Hao, Mingxuan Yuan
Graph Drawing Quality Estimation Logic Synthesis Hardware Description Language Biological Circuit Digital Circuit Apprenticeship Learning Verilog Textbook

October 28, 2024

Neuro-symbolic Learning Yielding Logical Constraints
Zenan Li, Yunpeng Huang, Zhaoyu Li, Yuan Yao, Jingwei Xu, Taolue Chen, Xiaoxing Ma, Jian Lu
Neural Topic Logic Synthesis Logical Constraint Symbolic System Symbol Grounding

September 16, 2024

Logic Synthesis Optimization with Predictive Self-Supervision via Causal Transformers
Raika Karimi, Faezeh Faez, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva
Causal Transformer Logic Synthesis Logic Design Logic Gate Benchmark Circuit

September 9, 2024

MTLSO: A Multi-Task Learning Approach for Logic Synthesis Optimization
Faezeh Faez, Raika Karimi, Yingxue Zhang, Xing Li, Lei Chen, Mingxuan Yuan, Mahdi Biparva
Multi Task Learning Electronic Design Automation Logic Synthesis Integrated Circuit Design

August 22, 2024

OPTDTALS: Approximate Logic Synthesis via Optimal Decision Trees Approach
Hao Hu, Shaowei Cai
Decision Tree Optimal Design Logic Synthesis Approximate Computing Circuit Complexity

August 19, 2024

ShortCircuit: AlphaZero-Driven Circuit Design
Dimitrios Tsaras, Antoine Grosnit, Lei Chen, Zhiyao Xie, Haitham Bou-Ammar, Mingxuan Yuan
Large Scale Circuit Circuit Design Logic Synthesis Biological Circuit Logic Design

June 7, 2024

Logic Synthesis with Generative Deep Neural Networks
Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang
Transformer Based Generative Neural Network Logic Synthesis

March 14, 2024

Circuit Transformer: End-to-end Circuit Design by Predicting the Next Gate
Xihan Li, Xing Li, Lei Chen, Xing Zhang, Mingxuan Yuan, Jun Wang
Transformer Based Transformer Based Model Deep Transformer Large Scale Circuit Circuit Design Logic Synthesis Circuit Model

March 2, 2024

Less is More: Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
Chenhui Deng, Zichao Yue, Cunxi Yu, Gokce Sarar, Ryan Carey, Rajeev Jain, Zhiru Zhang
Potential Scalability Graph Attention Self Attention Module Large Scale Circuit Logic Synthesis Learning Generalizable Circuit Representation

January 22, 2024

Retrieval-Guided Reinforcement Learning for Boolean Circuit Minimization
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan, Ramesh Karri, Siddharth Garg
Logic Synthesis Logic Minimization

January 19, 2024

BoolGebra: Attributed Graph-learning for Boolean Algebraic Manipulation
Yingjie Li, Anthony Agnesina, Yanqing Zhang, Haoxing Ren, Cunxi Yu
Logic Synthesis Logic Minimization Boolean Algebraic Manipulation

December 28, 2023

LLM4EDA: Emerging Progress in Large Language Models for Electronic Design Automation
Ruizhe Zhong, Xingbo Du, Shixiong Kai, Zhentao Tang, Siyuan Xu, Hui-Ling Zhen, Jianye Hao, Qiang Xu, Mingxuan Yuan, Junchi Yan
Much Progress Chip Design Electronic Design Automation Logic Synthesis Hardware Description Language

December 22, 2023

Adaptive Reconvergence-driven AIG Rewriting via Strategy Learning
Liwei Ni, Zonglin Yang, Jiaxi Zhang, Junfeng Liu, Huawei Li, Biwei Xie, Xinquan Li
Adaptive Importance Logic Synthesis Rewrite System Strategy Training Logic Minimization

October 16, 2023

Towards the Imagenets of ML4EDA
Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce, Ramesh Karri, Siddharth Garg
Supervised ImageNet Logic Synthesis Verilog Code Generation Hardware Platform Verilog Textbook

August 22, 2023

A Circuit Domain Generalization Framework for Efficient Logic Synthesis in Chip Design
Zhihai Wang, Lei Chen, Jie Wang, Xing Li, Yinqi Bai, Xijun Li, Mingxuan Yuan, Jianye Hao, Yongdong Zhang, Feng Wu
Large Scale Circuit Chip Design Logic Synthesis Circuit Representation Learning Domain Invariant Knowledge

August 7, 2023

GraPhSyM: Graph Physical Synthesis Model
Ahmed Agiza, Rajarshi Roy, Teodor Dumitru Ene, Saad Godil, Sherief Reda, Bryan Catanzaro
Electronic Design Automation Logic Synthesis Synthesis Procedure

May 25, 2023

DeepGate2: Functionality-Aware Circuit Representation Learning
Zhengyuan Shi, Hongyang Pan, Sadaf Khan, Min Li, Yi Liu, Junhua Huang, Hui-Ling Zhen, Mingxuan Yuan, Zhufei Chu, Qiang Xu
Logic Synthesis Logic Gate Circuit Representation Circuit Representation Learning Functional Learning

May 22, 2023

INVICTUS: Optimizing Boolean Logic Circuit Synthesis via Synergistic Learning and Search
Animesh Basak Chowdhury, Marco Romanelli, Benjamin Tan, Ramesh Karri, Siddharth Garg
Search Query Logic Synthesis Synergy Oriented LeARning Logic Minimization

March 6, 2023

ALMOST: Adversarial Learning to Mitigate Oracle-less ML Attacks via Synthesis Tuning
Animesh Basak Chowdhury, Lilas Alrahis, Luca Collini, Johann Knechtel, Ramesh Karri, Siddharth Garg, Ozgur Sinanoglu, Benjamin Tan
Adversarial Learning Logic Synthesis Recipe Generation