SRAM Cell

SRAM cells, the fundamental building blocks of static random-access memory, are undergoing intense research scrutiny to improve their performance and efficiency in various applications, particularly within the context of accelerating deep neural network computations. Current research focuses on optimizing SRAM architectures for processing-in-memory (PIM) paradigms, exploring techniques like algorithm-architecture co-design to maximize data capacity and developing novel methods for mitigating noise and aging effects. These advancements aim to enhance the speed, energy efficiency, and reliability of SRAM-based systems, impacting fields ranging from high-performance computing to resource-constrained edge devices.

Papers

July 18, 2024

Attention in SRAM on Tenstorrent Grayskull
Moritz Thüning
Human Attention Softmax Function Self Attention Layer SRAM Cell

January 11, 2024

Implications of Noise in Resistive Memory on Deep Neural Networks for Image Classification
Yannick Emonds, Kai Xi, Holger Fröning
Convolutional Neural Network Deep Neural Network Image Classification Industrial Disturbing Noise Future Implication Resistive Memory SRAM Cell

October 31, 2023

DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
Co Design Efficient Algorithm Processing in Memory Non Volatile Memory SRAM Cell

July 28, 2023

Seeking the Yield Barrier: High-Dimensional SRAM Evaluation Through Optimal Manifold
Yanfang Liu, Guohao Dai, Wei W. Xing
Yield Prediction Manifold Sampling Manifold Optimization SRAM Cell Corresponding Yield Stress Value

July 13, 2023

Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning
Leandro Lanzieri, Peter Kietzmann, Goerschwin Fey, Holger Schlarb, Thomas C. Schmidt
Machine Learning Internet of Thing Test Bed Failure Prediction Initialization Bias Age Datasets SRAM Cell

July 12, 2023

A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications
Xiaomeng Wang, Fengshi Tian, Xizi Chen, Jiakun Zheng, Xuejiao Liu, Fengbin Tu, Jie Yang, Mohamad Sawan, Kwang-Ting Cheng, Chi-Ying Tsui
Edge Intelligence Content Addressable Memory Signal Quality SRAM Cell Power Capacitor

May 12, 2023

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference
Lorenzo Sonnino, Shaswot Shresthamali, Yuan He, Masaaki Kondo
Scientific Inference Hardware Accelerator DNN Training Parallel Processing Processing in Memory SRAM Cell Memory Technology Common Belief

SRAM Cell

Papers

Attention in SRAM on Tenstorrent Grayskull

Implications of Noise in Resistive Memory on Deep Neural Networks for Image Classification

DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory

Seeking the Yield Barrier: High-Dimensional SRAM Evaluation Through Optimal Manifold

Ageing Analysis of Embedded SRAM on a Large-Scale Testbed Using Machine Learning

A 137.5 TOPS/W SRAM Compute-in-Memory Macro with 9-b Memory Cell-Embedded ADCs and Signal Margin Enhancement Techniques for AI Edge Applications

DAISM: Digital Approximate In-SRAM Multiplier-based Accelerator for DNN Training and Inference