Systolic Array

Systolic arrays are parallel processing architectures designed to efficiently perform matrix multiplications, crucial for accelerating deep neural network (DNN) inference and training, particularly for convolutional neural networks (CNNs) like VGG and ResNet. Current research focuses on optimizing dataflow within these arrays (e.g., triangular input movement) to minimize memory access and energy consumption, improving reliability through fault tolerance techniques and efficient monitor placement, and developing adaptable architectures that handle both dense and sparse matrix operations with variable precision. These advancements are significantly impacting the performance and energy efficiency of DNN accelerators, enabling faster and more power-efficient AI applications.

Papers

November 15, 2024

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems
Pedro Palacios, Rafael Medina, Jean-Luc Rouas, Giovanni Ansaloni, David Atienza
Transformer Megatron Decepticons High Efficiency Speech Recognition Structured Pruning Edge Server Systolic Array

August 5, 2024

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part II: Architecture and Hardware Implementation
Cristian Sestito, Shady Agwa, Themis Prodromakis
Convolutional Neural Network Field Programmable Gate Array Architecture Design FPGA Accelerator Hardware Implementation Systolic Array

August 2, 2024

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part I: Dataflow and Analytical Modelling
Cristian Sestito, Shady Agwa, Themis Prodromakis
Convolutional Neural Network Different PaRT Mathematical Model Dataflow Architecture Representation Bottleneck Systolic Array

January 17, 2024

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators
Mahdi Taheri, Natalia Cherezova, Mohammad Saeed Ansari, Maksim Jenihhin, Ali Mahani, Masoud Daneshtalab, Jaan Raik
Environment Exploration DNN Accelerator System Reliability Systolic Array

November 28, 2023

Monitor Placement for Fault Localization in Deep Neural Network Accelerators
Wei-Kai Liu
Deep Neural Network DNN Accelerator Sensor Placement Deep Learning Accelerator Systolic Array

June 29, 2023

Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations
Hadi Esmaeilzadeh, Soroush Ghodrati, Andrew B. Kahng, Sean Kinzer, Susmita Dey Manasi, Sachin S. Sapatnekar, Zhiang Wang
Training Data Direct Convolution Convolution Layer Performance Analysis Convolution Operation DNN Inference Systolic Array

April 17, 2023

Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite
Jose Nunez-Yanez, Andres Otero, Eduardo de la Torre
Hardware Accelerator Self Reconfiguration Systolic Array Single Core Tensorflow Lite

December 6, 2022

Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework
F. N. Peccia, O. Bringmann
Hardware Accelerator Phantom 2D Accelerator Auto Tuning Systolic Array Heterogeneous System on Chip Custom Accelerator

November 22, 2022

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining
C. Peltekis, D. Filippas, G. Dimitrakopoulos, C. Nicopoulos, D. Pnevmatikatos
Systolic Array

June 30, 2022

Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators
Jung Hwan Heo, Arash Fayyazi, Amirhossein Esmaili, Massoud Pedram
CNN Accelerator Multi Accelerator Sparsity Pattern Deep Learning Compiler Efficient Compilation Systolic Array Systolic Complex Power Dissipation

March 22, 2022

Scale-out Systolic Arrays
Ahmet Caner Yüzügüler, Canberk Sönmez, Mario Drumond, Yunho Oh, Babak Falsafi, Pascal Frossard
Inference Accelerator Multi Accelerator Systolic Array

Systolic Array

Papers

Systolic Arrays and Structured Pruning Co-design for Efficient Transformers in Edge Systems

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part II: Architecture and Hardware Implementation

TrIM: Triangular Input Movement Systolic Array for Convolutional Neural Networks -- Part I: Dataflow and Analytical Modelling

Exploration of Activation Fault Reliability in Quantized Systolic Array-Based DNN Accelerators

Monitor Placement for Fault Localization in Deep Neural Network Accelerators

Performance Analysis of DNN Inference/Training with Convolution and non-Convolution Operations

Dynamically Reconfigurable Variable-precision Sparse-Dense Matrix Acceleration in Tensorflow Lite

Integration of a systolic array based hardware accelerator into a DNN operator auto-tuning framework

ArrayFlex: A Systolic Array Architecture with Configurable Transparent Pipelining

Sparse Periodic Systolic Dataflow for Lowering Latency and Power Dissipation of Convolutional Neural Network Accelerators

Scale-out Systolic Arrays