Verilog Code Generation

Verilog code generation research focuses on automating the creation of hardware description language (HDL) code using artificial intelligence, primarily large language models (LLMs). Current efforts concentrate on improving the syntactic and functional correctness of generated Verilog, employing techniques like fine-tuning on specialized datasets, multi-expert architectures, and incorporating feedback mechanisms such as golden code comparisons or generative discriminators. This research aims to accelerate and improve the efficiency of hardware design, reducing errors and development time, with significant implications for the integrated circuit (IC) design industry.

Papers

November 5, 2024

MetRex: A Benchmark for Verilog Code Metric Reasoning Using LLMs
Manar Abdelatty, Jingxiao Ma, Sherief Reda
Large Language Model New Benchmark Verilog Code Generation Abstraction Based VHDL Code

September 23, 2024

Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
Bingkun Yao, Ning Wang, Jie Zhou, Xi Wang, Hong Gao, Zhe Jiang, Nan Guan
Large Language Model Location Information Verilog Code Generation Functional Verilog Description BUG Localization Verilog Textbook

August 19, 2024

Are LLMs Any Good for High-Level Synthesis?
Yuchao Liao, Tosiron Adegbija, Roman Lysecky
Large Language Model High Performance Computing High Level Synthesis Verilog Code Generation

August 15, 2024

VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool
Chia-Tung Ho, Haoxing Ren, Brucek Khailany
Abstract Syntax Tree Verilog Code Generation Waveform Model Graph Based Planning Functional Verilog Description

July 21, 2024

July 15, 2024

CodeV: Empowering LLMs for Verilog Generation through Multi-Level Summarization
Yang Zhao, Di Huang, Chongxiao Li, Pengwei Jin, Ziyuan Nan, Tianyun Ma, Lei Qi, Yansong Pan, Zhenxing Zhang, Rui Zhang, Xishan Zhang, Zidong Du, Qi Guo, Xing Hu, Yunji Chen
Large Language Model Hardware Description Language Verilog Code Generation Single Document Summarization Functional Verilog Description Design Automation

July 11, 2024

Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation
Kaiyan Chang, Zhirong Chen, Yunhao Zhou, Wenlong Zhu, kun wang, Haobo Xu, Cangyuan Li, Mengdi Wang, Shengwen Liang, Huawei Li, Yinhe Han, Ying Wang
Generative AI Natural Language High Level Synthesis Verilog Code Generation

May 27, 2024

RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
Ahmed Allam, Mohamed Shalan
Large Language Model New Benchmark Verilog Code Generation Register Transfer Level

April 11, 2024

A Multi-Expert Large Language Model Architecture for Verilog Code Generation
Bardia Nadimi, Hao Zheng
Verilog Code Generation Functional Verilog Description LLM RBMT Expert Language Model Design Knowledge

March 17, 2024

Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework
Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang, Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, yinhe han, Huawei Li, Xiaowei Li
Large Language Model Raw Data Chip Design Electronic Design Automation Hardware Description Language Verilog Code Generation Iterative Design

February 3, 2024

BetterV: Controlled Verilog Generation with Discriminative Guidance
Zehua Pei, Hui-Ling Zhen, Mingxuan Yuan, Yu Huang, Bei Yu
Electronic Design Automation Hardware Description Language Verilog Code Generation Functional Verilog Description Discriminator Guidance

October 16, 2023

Towards the Imagenets of ML4EDA
Animesh Basak Chowdhury, Shailja Thakur, Hammond Pearce, Ramesh Karri, Siddharth Garg
Supervised ImageNet Logic Synthesis Verilog Code Generation Hardware Platform Verilog Textbook

September 14, 2023

VerilogEval: Evaluating Large Language Models for Verilog Code Generation
Mingjie Liu, Nathaniel Pinckney, Brucek Khailany, Haoxing Ren
Synthetic Instruction Verilog Code Generation

July 28, 2023

VeriGen: A Large Language Model for Verilog Code Generation
Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, Siddharth Garg
Large Language Model Verilog Code Generation Design Automation Verilog Textbook

April 26, 2023

A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation
Enrique Dehaerne, Bappaditya Dey, Sandip Halder, Stefan De Gendt
Product Design Deep Learning Framework Hardware Description Language Verilog Code Generation Functional Verilog Description Verilog Textbook

December 13, 2022

Benchmarking Large Language Models for Automated Verilog RTL Code Generation
Shailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg
Verilog Code Generation Functional Verilog Description Verilog Textbook