Paper ID: 2203.00655

A hardware-software co-design approach to minimize the use of memory resources in multi-core neuromorphic processors

Vanessa R. C. Leite, Zhe Su, Adrian M. Whatley, Giacomo Indiveri

Both in electronics and biology, physical implementations of neural networks have severe energy and memory constraints. We propose a hardware-software co-design approach for minimizing the use of memory resources in multi-core neuromorphic processors, by taking inspiration from biological neural networks. We use this approach to design new routing schemes optimized for small-world networks and to provide guidelines for designing novel application-specific multi-core neuromorphic chips. Starting from the hierarchical routing scheme proposed, we present a hardware-aware placement algorithm that optimizes the allocation of resources for arbitrary network models. We validate the algorithm with a canonical small-world network and present preliminary results for other networks derived from it.

Submitted: Mar 1, 2022