HiAER-Spike Software-Hardware Reconfigurable Platform for Event-Driven Neuromorphic Computing at Scale
Authors: Gwenevere Frank, Gopabandhu Hota, Keli Wang, Christopher Deng, Krish Arora, Diana Vins, Abhinav Uppal, Omowuyi Olajide, Kenneth Yoshimoto, Qingbo Wang, Mari Yamaoka, Johannes Leugering, Stephen Deiss, Leif Gibb, Gert Cauwenberghs
Organizations: Institute for Neural Computation, UC San Diego, 9500 Gilman Dr, La Jolla, 92093, CA, USA. · Qernel AI, 460 California Ave ste 204, Palo Alto, 94306, CA, USA. · Fujitsu, 4-1-1 Kamikodanaka, Nakahara-ku Kawasaki-shi, 211-8588, Kanagawa, Japan. · Forschungszentrum Jülich, 52425, Jülich, Germany.
In this work, we present HiAER-Spike, a modular, reconfigurable, event-driven neuromorphic computing platform designed to execute large spiking neural networks with up to 160 million neurons and 40 billion synapses - roughly twice the neurons of a mouse brain at faster than real time. This system, assembled at the UC San Diego Supercomputer Center, comprises a co-designed hard- and software stack that is optimized for run-time massively parallel processing and hierarchical address-event routing (HiAER) of spikes while promoting memory-efficient network storage and execution. The architecture efficiently handles both sparse connectivity and sparse activity for robust and low-latency event-driven inference for both edge and cloud computing. A Python programming interface to HiAER-Spike, agnostic to hardware-level detail, shields the user from complexity in the configuration and execution of general spiking neural networks with minimal constraints in topology. The system is made easily available over a web portal for use by the wider community. In the following, we provide an overview of the hard- and software stack, explain the underlying design principles, demonstrate some of the system's capabilities and solicit feedback from the broader neuromorphic community. Examples are shown demonstrating HiAER-Spike's capabilities for event-driven vision on benchmark CIFAR-10, DVS event-based gesture, MNIST, and Pong tasks.
Figures & tables
Figure 1: High-level system architecture of HiAER-Spike. (a) Neurons and synapses form the ‘grey matter’ of dense local interconnects in the system while long-range connections (between cores and FPGAs) form the ‘white matter’ of sparse global interconnects. (b) The hardware equivalent of (a) as implemented in our multi-core architecture on the FPGA. The grey matter inside each core is implemented as sequentially updated integrate-and-fire neurons, whose internal state is stored in neural membrane registers in URAM, whereas spike events are routed through synaptic look-up tables in HBM. The white matter is implemented as a hierarchical multicast bus (HiAER) interconnecting axon spike register modules that are stored in BRAM across cores.
Figure 2: (a) Host programming interface with SNN compiler and low-level hardware interface. (b) Heterogeneous memory organization within a single core, as well as the off-chip HBM storing the synaptic connectivity table. On-chip URAM and BRAM store state variables of axons and neurons. The top-left panel shows the layout of the data structure in HBM, supporting parallelism of 16 neurons per single core.
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Figure 3: DVS Gesture example. Representation of a waving gesture frame processed into two 63×63 pixel channels corresponding to ON and OFF events, with overlapped visualization showing ON events (green), OFF events (red), and overlapping ON and OFF events (yellow). One of ten frames accumulated across a gesture.
Figure 4: A 160x210-pixel Atari Pong frame (left) and the DVS representation of that frame (right) processed into two 84×84-pixel channels corresponding to ON and OFF events, with overlapped visualization showing ON events (green) and OFF events (red), detecting 27 OFF and 28 ON events in the current frame. The location of green ON pixels relative to red OFF pixels indicates the direction of motion (e.g. the ball in the center is moving diagonally towards the lower right).
Figure 5: Test accuracy of the DVS gesture network compared across different model sizes and full-precision software models, quantized software models, and hardware.
System
Model Size (Neurons)
Accuracy (%)
Energy ( \mathchar28950\mathchar29002 )
Latency ( \mathchar28950\mathchar29043 )
HiAER-Spike
138
96.59
1.1
4.2
HiAER-Spike
5,814
98.14
17.1
48.6
Loihi Lenz et al. (2023)
5,400
99.23
182.46
4,900
SpiNNaker Stromatias et al. (2015)
1,790
95.01
N/A
20,000
TrueNorth Esser et al. (2015)
7,680*
99.42
108
N/A
MNIST Comparison Across Neuromorphic Platforms
System
Model Size (Neurons)
Accuracy (%)
Energy ( \mathchar28950\mathchar29002 )
Latency ( \mathchar28950\mathchar29043 )
HiAER-Spike
1,115
54.51
79.8
184.9
HiAER-Spike
17,709
68.75
510.7
1,156.2
Loihi Massa et al. (2020)
N/A
89.64
N/A
11,430
SpiNNaker2 Arfa et al. (2025)
9,907
94.13
459,000
N/A
TrueNorth Amir et al. (2017)
N/A
96.49
18,700
104,600
DVS Gesture Comparison Across Neuromorphic Platforms
Appendix figures & tables4 assets
Supplementary material from the paper’s appendix.
Appendix
Figure 6: Example network and generating code.
Figure 7: Simplified flowchart describing the process of mapping a network into the HBM synaptic routing table.
Figure 9: The HiAER-Spike system as implemented at the San Diego Supercomputer Center, consisting of 6 servers, one coordinating the system and the other five each containing 8 FPGAs. FPGAs within a server are connected together using FireFly cables, and FPGAs will be connected between servers using a custom Ethernet protocol. Three Arista switches service the system; the Arista 7170 will implement the custom Ethernet routing protocol.
Figure 10: The relationship between HBM energy/latency per inference and the number of neurons for three different model types run on a single FPGA core: MLP, LeNet-5, and DVS Gesture spiking CNN. HBM energy/latency per inference scales linearly with the number of neurons in a model. The linear fits calculate the approximate increase in HBM energy/latency per inference for each additional neuron. The HBM energy and latency cost per neuron depends on the specific model architecture and type. The MLP models cost about 2.4 times more HBM energy and 2.2 times more latency per neuron than the LeNet-5, likely attributable to the larger number of connections per neuron (for most neurons) in MLP models. The DVS Gesture spiking CNN models cost about 10.5 times more HBM energy and 9.5 times more latency per neuron than the LeNet-5, likely attributable to the use of 10 frames per inference (requiring 10 timesteps) for the spiking CNN models.
In deep learning, efficiency gets more and more important to compensate for the ongoing growth in model sizes and applications. Neuromorphic hardware has long been advocated as an upcoming alternative to deep networks, taking inspiration from the brain for achieving unprecedented energy efficiency. However, demonstrations of these gains only recently began to grow in complexity and real-world applicability. With SpiNNaker2, we present a chip that bridges the gap between deep networks and neuromorphic computing and allows for flexible exploration of computing approaches that combine both worlds. It features 152 processing elements equipped with an ARM M4F processor and dedicated accelerators, an extended SpiNNaker routing fabric for scalable event-based communication and a range of external interfaces for system integration, including Gbit Ethernet and an LPDDR4 memory interface. We demonstrate performance and efficiency of the SpiNNaker2 chip for neuromorphic and deep network workloads, as well as novel event-based computing approaches. For deep network workloads, the chip achieves up to 4.5 TOPS in high performance mode and up to 2.7 TOPS/W efficiency in high efficiency mode for INT8 workloads. The chip supports spiking neural networks with >150000 neurons and >1.8 billion synaptic events/s when simulated with a 1 ms time step. Its low baseline power of less than 250 mW allows for efficiency even under varying workload conditions, allowing to explore sparse and event-based modes of computation. All this demonstrates the chip's capabilities as a universal hardware platform for scalable brain-inspired computing and its combinations with mainstream deep network approaches.
Stefan Scholze, Johannes Partzsch, Sebastian Höppner +27
Chair of Highly-Parallel VLSI-Systems and Neuro-Microelectronics, Technische Universität Dresden, Germany · Centre for Tactile Internet with Human-in-the-loop (CeTI) · Advanced Processor Technologies Group, Department of Computer Science, University of Manchester, UK +2
Many-core neuromorphic systems accelerate Spiking Neural Networks (SNNs), yet their packet-based spike communication can spend substantial traffic and energy repeatedly transmitting destination addresses. This overhead is amplified by the small payload of spike packets: in representative workloads, duplicate address transmissions account for up to 49% of the total traffic. This paper presents UniSpike, a hardware-software co-design that removes address redundancy by aggregating spikes destined for the same core into compact packets. UniSpike combines destination-centric spike scheduling, lightweight runtime packet assembly hardware, and destination-aware SNN partitioning. Across diverse SNN workloads, UniSpike reduces traffic by 1.93× on average, delivering 1.77× speedup and 1.50× energy efficiency improvement over state-of-the-art designs.
Spiking neural networks (SNNs) are a promising paradigm for energy-efficient event-driven computation, but large-scale SNN execution remains challenging because sparse spike communication and synchronization can dominate runtime. Existing solutions across CPU, GPU, ASIC, and FPGA platforms offer different trade-offs between programmability, efficiency, and scalability. To address this gap, we present NeuroRing, a modular and scalable SNN accelerator based on a stream-dataflow architecture and a bidirectional ring topology, implemented in High-Level Synthesis (HLS) on FPGAs. NeuroRing supports modular single- and multi-FPGA deployment and is compatible with existing SNN workflows through integration with the NEST simulator. We evaluate NeuroRing on the cortical microcircuit benchmark and a Sudoku constraint-satisfaction workload. Results show that NeuroRing preserves the key activity statistics of the NEST reference model, achieves faster-than-real-time execution of the full-scale cortical microcircuit with a real-time factor (RTF) of 0.83, exhibits meaningful strong and weak scaling, and provides competitive energy efficiency on two programmable FPGAs. These results position NeuroRing as a flexible and scalable platform for both neuroscience simulation and broader event-driven applications.
Muhammad Ihsan Al Hafiz, Artur Podobas
KTH Royal Institute of Technology, Stockholm, Sweden