SlideSparse: Fast and Flexible (2N-2):2N Structured Sparsity
Authors: Hanyong Shao, Yingbo Hao, Ting Song, Yan Xia, Di Zhang, Shaohan Huang, Xun Wu, Songchen Xu, Le Xu, Li Dong, Zewen Chi, Yi Zou, Furu Wei
Organizations: Peking University · Microsoft Research · South China University of Technology · Shanghai Jiao Tong University · The Hong Kong University of Science and Technology
NVIDIA's 2:4 Sparse Tensor Cores deliver 2x throughput but demand strict 50% pruning -- a ratio that collapses LLM reasoning accuracy (Qwen3: 54% to 15%). Milder (2N−2):2N patterns (e.g., 6:8, 25% pruning) preserve accuracy yet receive no hardware support, falling back to dense execution without any benefit from sparsity. We present SlideSparse, the first system to unlock Sparse Tensor Core acceleration for the (2N−2):2N model family on commodity GPUs. Our Sliding Window Decomposition reconstructs any (2N−2):2N weight block into N−1 overlapping 2:4-compliant windows without any accuracy loss; Activation Lifting fuses the corresponding activation rearrangement into per-token quantization at near-zero cost. Integrated into vLLM, SlideSparse is evaluated across various GPUs (A100, H100, B200, RTX 4090, RTX 5080, DGX-spark), precisions (FP4, INT8, FP8, BF16, FP16), and model families (Llama, Qwen, BitNet). On compute-bound workloads, the measured speedup ratio (1.33x) approaches the theoretical upper-bound N/(N−1)=4/3 at 6:8 weight sparsity in Qwen2.5-7B, establishing (2N−2):2N as a practical path to accuracy-preserving LLM acceleration. Code available at https://github.com/bcacdwk/vllmbench.
Figures & tables
Figure 1: SlideSparse extends 2:4 Sparse Tensor Cores to the (2N−2):2N sparsity family. (a) SlideSparse transforms 6:8 weights into 2:4-compliant blocks, enabling sparsity acceleration. (b) End-to-end speedup on A100 (INT8, seq_len = 8K) approaches the theoretical limit Smax=N/(N−1)=3/2,4/3,5/4,... (§ 3 ).
Figure 2: Reasoning accuracy of Qwen3 ( Yang et al., 2025 ) under different sparsity. 6:8 preserves near-dense performance (51.6% vs. 54.0%); 2:4 collapses to 15.3%.
Figure 3: Two-dimensional compression space for LLM acceleration. X-axis: quantization precision (16-bit to 1.58-bit BitNet, up to 8× speedup). Y-axis: sparsity (dense to 2:4, up to 2× speedup). Gray dots mark existing hardware support—limited to dense or 2:4 extremes. Green dots show (2N−2):2N patterns that SlideSparse enables, filling the Acceleration Gap and unlocking fine-grained sparsity–precision trade-offs.
Figure 4: Sliding window decomposition for 6:8 sparsity. Three stride-2 windows (each size 4) cover all 8 positions. Overlap regions allow non-zeros to spill into the next windows when one reaches capacity, converting any (2N−2):2N pattern into concatenated 2:4 blocks for Sparse Tensor Core acceleration.
Figure 5: SlideSparse system overview. Offline : Weight preprocessing transforms (2N−2):2N sparse weights into slided format with γ× expansion. Initialization : cuSPARSELt compresses weights into 2:4 format at model load time. Online : Per-request inference executes fused quantization-slide kernel followed by sparse GEMM.
Figure 6: Kernel-level speedup at M=16384 across varied precisions and GPUs. Top row: B200 (INT8, FP8, BF16); Bottom row: A100 INT8, RTX 4090 FP8, RTX 5080 BF16. B200 INT8 achieves 4 – 6× due to suboptimal cuBLASLt INT8 performance on Blackwell; other configurations approach theoretical Seff bounds. Comprehensive kernel results are shown in Appendix D.3 .
Figure 7: Kernel speedup vs. M on A100 and B200 (Qwen-7B, INT8). (a) A100: speedup increases with M , approaching the theoretical limit for 6:8. (b) B200: consistently high speedup across all M (note different Y-axis scale).
Figure 10: Speedup vs. M on B200 (Qwen-7B, INT8). (a) Decode ( M∈{128,256,512} ); (b) Prefill ( M∈{4K,8K,16K,32K} ). All (2N−2):2N patterns achieve consistent speedups across M .
Appendix figures & tables2 assets
Supplementary material from the paper’s appendix.
Appendix
GPU
M
Quant-only
Quant+Slide
Overhead
Δ ( μ s)
A100
2048
18.4
27.7
+50%
9.3
A100
4096
30.7
44.0
+43%
13.3
A100
8192
60.4
77.8
+29%
17.4
A100
16384
109.6
141.3
+29%
31.7
H100
4096
26.6
34.7
+30%
8.1
H100
8192
47.3
64.2
+36%
16.9
Appendix
Table 1: Fused kernel latency ( μ s) for 6:8 sparsity. Overhead is relative to quant-only baseline.
GPU
Arch.
CC
Memory
Platform
Host Arch.
A100 80GB PCIe
Ampere
sm80
80GB HBM2e
Datacenter
x86_64
H100 80GB PCIe
Hopper
sm90
80GB HBM3
Datacenter
x86_64
B200 180GB SXM
Blackwell
sm100
180GB HBM3e
Datacenter
x86_64
RTX 4090
Ada Lovelace
sm89
24GB GDDR6X
Consumer
x86_64
RTX 5080
Blackwell
sm120
16GB GDDR7
Consumer
x86_64
DGX Spark (GB10)
Blackwell
sm121
128GB Unified
Embedded
aarch64
Appendix
Table 2: Hardware specifications for all evaluated GPUs.
LLM inference acceleration develops algorithms and systems that reduce language-model latency, memory use, and serving cost while preserving output quality.
Semi-structured 2:4 sparsity is widely supported by modern accelerators, providing up to a 2x theoretical speedup. However, its strict 50% sparsity constraint often causes non-negligible accuracy degradation under post-training pruning. Meanwhile, existing relaxed sparsity formats either require specialized compiler support or introduce runtime overheads that limit end-to-end speedup. We propose Spense, a practical hybrid sparse-dense format that splits each weight matrix into a 2:4 sparse region and a dense region. This design relaxes the effective sparsity constraint while remaining compatible with existing high-performance sparse and dense GEMM libraries, avoiding both custom compiler support and input activation expansion. Building on this format, we introduce SpenseGPT, a one-shot post-training pruning method that produces sparse and dense regions. Notably, we show that selecting the right dense regions is important, and we devise two different strategies to choose them. Experiments on Qwen3-32B and Seed-OSS-36B demonstrate that our method achieves up to 1.2x end-to-end decoding speedup on B200 GPUs with FP8 precision, while preserving accuracy. To the best of our knowledge, this is the first one-shot pruning demonstration of real-world end-to-end LLM decoding speedup from semi-structured sparse tensor cores on recent GPUs such as B200s, while maintaining model quality.
Jaeseong Lee, Seung-won Hwang, Samyam Rajbhandari
Snowflake AI Research* · Seoul National University†
NVIDIA tensor cores have supported 2:4 semi-structured sparsity since Ampere, and the pattern composes with quantization. When the two are combined, the practical question is which step to take next: from a given precision, add 2:4 sparsity or drop to the next lower precision? We compare the two at equal bits, with sparsity metadata counted, and at equal nominal tensor-core tiers, over all six GEMM operands of a transformer layer, with kernels measured on three GPU generations and online pruning and quantization included. Our results show that as long as a lower precision is available, adding 2:4 is the worse step, both less accurate and slower, because the energy that 2:4 discards from each group of four along the hardware-forced axis does not shrink with bits, while quantization error does. Once quantization reaches the lowest precision the hardware supports, 2:4 still speeds up linear layers by 1.3--1.7\x{}, and on an H100 a retrained 2:4 model served in FP8 by vLLM reaches 27% higher prefill throughput than the dense FP8 model, with GSM8K accuracy on par. Its quality has to be won back by retraining, however, which restores perplexity long before reasoning; on Blackwell, whose sparse FP4 uses a pairwise 4:8 pattern, the loss is larger and our retraining budget did not recover it.
Large language models (LLMs) deliver impressive performance but incur prohibitive memory and compute costs at deployment. Model pruning is an effective way to reduce these overheads, yet existing approaches face challenges: unstructured sparsity, where nonzeros can appear anywhere, preserves accuracy but yields irregular access patterns that prevent GPU acceleration, while semi-structured 2:4 sparsity is hardware-friendly but enforces a rigid 50% pattern that degrades model quality. To bridge this gap, we introduce PATCH, a hybrid sparsity framework that enables a continuous sparsity ratio between 0% and 50%. PATCH partitions weight matrices into tiles, assigning each tile to be either dense or 2:4 sparse via a learnable mask selection mechanism. This design provides fine-grained control over accuracy-acceleration tradeoffs and supports non-uniform sparsity across layers, leading to superior overall quality. Across models from 0.5B to 13B parameters, PATCH consistently narrows the gap to dense accuracy while delivering practical speedups. For instance, on LLaMA-2 7B with an A6000 GPU, PATCH achieves 1.18x-1.38x end-to-end speedup over dense baselines while improving accuracy by 0.37%-2.96% compared to the state-of-the-art 2:4 pruning method, MaskLLM.
Younes Hourri, Mohammad Mozaffari, Maryam Mehri Dehnavi
Department of Computer Science University of Toronto