Traditional machine learning depends on high-precision arithmetic and near-ideal hardware assumptions, which is increasingly challenged by variability in aggressively scaled semiconductor devices. Compute-in-memory (CIM) architectures alleviate data-movement bottlenecks and improve energy efficiency yet introduce nonlinear distortions and reliability concerns. We address these issues with a hardware-aware optimization framework based on Hyperdimensional Computing (HDC), systematically compensating for non-ideal similarity computations in CIM. Our approach formulates encoding as an optimization problem, minimizing the Frobenius norm between an ideal kernel and its hardware-constrained counterpart, and employs a joint optimization strategy for end-to-end calibration of hypervector representations. Experimental results demonstrate that our method when applied to QuantHD achieves 84% accuracy under severe hardware-induced perturbations, a 48% increase over naive QuantHD under the same conditions. Additionally, our optimization is vital for graph-based HDC reliant on precise variable-binding for interpretable reasoning. Our framework preserves the accuracy of RelHD on the Cora dataset, achieving a 5.4× accuracy improvement over naive RelHD under nonlinear environments. By preserving HDC's robustness and symbolic properties, our solution enables scalable, energy-efficient intelligent systems capable of classification and reasoning on emerging CIM hardware.
Figures & tables
Figure 1. High-level overview of how our optimization framework bridges brain-inspired hyperdimensional computing and next-generation computing-in-memory architectures. Our optimization framework ensures that core hyperdimensional operations (binding, bundling, and associative search) remain robust despite the nonlinearity inherent to emerging semiconductor devices. This approach supports both classification and graph-based reasoning, laying the foundation for energy-efficient AI reasoning systems.
Ref.
Speedup
Energy efficiency
RelHD vs 1080Ti ( Kang et al., 2022 )
33x
59287x
FeReX vs 3090Ti ( Xu et al., 2024 )
250x
18000x
MIMHD vs 1080 ( Kazemi et al., 2021 )
56x
314x
Table 1. HDC speedup
Figure 2. Hardware-aware HDC using our joint-optimization framework. The system optimizes encoding under nonlinear constraints from CiM hardware, ensuring robust associative search and reasoning through kernel optimization.
Figure 3. (a) are the kernel shapes under only nonlinear associative search while (b) are the kernel heatmaps under both nonlinear encoding and associative search process. (A) represents the original desired kernel (B) shows HDC kernel approximation (C) is the similarity-optimized HDC approximation (D) is our proposed joint optimization kernel approximation. Two side-by-side visualizations: one showing kernel shapes under nonlinear associative search, and one showing heatmaps under nonlinear associative search and encoding.
Figure 4. GrapHD-based Graph reconstruction under hardware nonlinearity and noise. We see that a (B) GrapHD under hardware-induced nonlinearity fails to reconstruct the true graph as it is not able to classify edges between nodes properly. (C) Our optimization allows GrapHD to work even under nonlinearity.
Figure 5. Our proposed HDC optimization for HDC classification compared to naive HDC implementation on noisy Hardware. The dotted represents QuantHD’s normal performance on Isolet and FMNIST datsets.
Figure 6. Similarity distributions between nodes for (A) GrapHD (B) GrapHD under Nonlinearity (C) Optimized GrapHD under Nonlinearity. Our optimization gives GrapHD a similar distribution even under hardware constraints while (B) has an extremely narrow distribution centered around 1. A visualization of GrapHD's similarity distribution under normal and nonlinearity
Figure 7. Our proposed optimization for RelHD compared to naive RelHD implementation on noisy hardware. The dotted line represents the RelHD performance under normal environments.
As Moore's law reaches its physical and economic limits, domain-specific approaches are increasingly employed to accelerate machine learning workloads. Hyperdimensional Computing (HDC) represents one such emerging paradigm, offering an alternative to conventional deep learning techniques. Rooted in cognitive models of computation, HDC is designed bottom-up with hardware efficiency as a first-class objective. HDC workloads map naturally to heterogeneous hardware platforms, including CPUs, GPUs, and FPGAs, as well as emerging in-memory computing technologies such as Resistive RAM (ReRAM) and Phase-Change Memory (PCM). HDC algorithms are intrinsically tolerant to noise and approximation, enabling substantial performance gains with minimal accuracy loss. In this work, we introduce ApproxHDC, a framework for automated identification and application of domain-specific approximations in HDC workloads. ApproxHDC extends the HPVM-HDC compiler infrastructure to enable retargetable compilation across diverse hardware backends, including CPUs, GPUs, and simulated ReRAM and PCM-based accelerators. The space of possible approximations is exponentially large; ApproxHDC employs efficient search and analysis to navigate it and identify high-impact configurations spanning both software and hardware levels.
Xavier Routh, Abdul Rafae Noor, Akash Kothari +4
University of Illinois Urbana-Champaign Urbana, IL, USA · University of California San Diego La Jolla, CA, USA
Overparameterized machine learning (ML) methods such as neural networks may be prohibitively resource intensive for devices with limited computational capabilities. Hyperdimensional computing (HDC) is an emerging resource efficient and low-complexity ML method that allows hardware efficient implementations of (re-)training and inference procedures. In this paper, we propose a maximum-margin HDC classifier, which significantly outperforms baseline HDC methods on several benchmark datasets. Our method leverages a formal relation between HDC and support vector machines (SVMs) that we established for the first time. Our findings may inspire novel HDC methods with potentially more hardware-oriented implementations compared to SVMs, thus enabling more efficient learning solutions for various intelligent resource-constrained applications.
Nikita Zeulin, Olga Galinina, Ravikumar Balakrishnan +2
Tampere University, Tampere, Finland · Tampere Institute for Advanced Study, Tampere University, Finland · Intel Corporation, Santa Clara, CA, United States
Hyperdimensional computing (HDC) is attractive for efficient and robust learning, but conventional inference still encodes every query independently, repeatedly paying the cost of high-dimensional projection. We introduce SupHDC, a new inference paradigm that processes multiple queries through a shared encoding computation. SupHDC assigns lightweight random slot keys, superposes the keyed queries before encoding, and uses slot-specific classifiers to recover their individual predictions. A random-feature kernel view explains why exact recovery of each hypervector is unnecessary: inference only needs to preserve the class evidence that determines the prediction. Across ten datasets, SupHDC achieves 1.39x analytical speedup with no average accuracy loss, and up to 2.08x speedup with only a 2.67 percentage-point mean accuracy loss. On a Raspberry Pi~5, it delivers 2.01x measured wall-clock speedup with a 2.26 percentage-point loss in mean prediction accuracy. SupHDC shows that high-dimensional redundancy can be used not only for robustness, but also as capacity for shared inference.