SweepLSD: A One-Pass, O(width)-Memory Line Segment Detector with an Integer-Only Streaming Core and a Real-Time FPGA Realization

Line segment detection has been studied for decades, yet existing methods are typically designed for different detection paradigms. Generic line segment detectors aim to recover all meaningful line segments in an image, whereas recent deep-learning-based approaches mainly target wireframe line segments that describe salient geometric structures. Because these paradigms follow different detection objectives, methods optimized for one often perform poorly on the other. In this work, we propose Adaptive Dual-Constrained Line Aggregation (ADLA), a line extraction framework designed to operate across different line segment detection paradigms. Starting from an edge strength map, ADLA progressively aggregates pixels into candidate line segments under two complementary geometric constraints: orientation coherence and bounded orthogonal distance to an adaptively estimated line model. During aggregation, the line centroid and orientation are dynamically updated using the accumulated supporting pixels, progressively improving the geometric consistency of the estimated line. Edge strength information is further incorporated into orientation estimation, seed selection, model refinement, and segment validation, reducing the need for extensive parameter tuning. Experiments on three publicly available datasets covering generic, wireframe, and Manhattan line segment detection demonstrate consistently strong performance across substantially different annotation settings. ADLA achieves (F^H) scores of 0.8665 on YorkUrban-LineSegment dataset, 0.8720 on ShanghaiTech dataset, and 0.7297 on YorkUrban dataset. These results demonstrate the effectiveness and flexibility of ADLA across different line segment detection paradigms. The source code for this work is publicly available at https://github.com/ChenguangTelecom/adla .

Line segment detection is a key building block in visual SLAM, 3D reconstruction, and industrial inspection. Recent deep learning methods have greatly improved accuracy, yet even the smallest models require several megabytes of memory, exceeding low-cost MCU capacity. This work investigates the maximum achievable accuracy under a sub-megabyte budget. We propose MiLSD, a detector tailored for MCU-level constraints, and systematically compare three output representations within a compact fully-convolutional backbone. Our study shows that the proposed F-Clip center-with-length-and-angle formulation learns most effectively at small model sizes. We find that 8-bit quantization preserves full-precision performance, while 4-bit quantization causes significant degradation, particularly in angle regression, with quantization-aware training recovering only part of the loss. With a one-megabyte activation budget and inference enhancements including sub-pixel decoding, test-time augmentation, and a lightweight verifier, MiLSD improves sAP10 on ShanghaiTech Wireframe from 10.6 (25k parameters, 0.25 MB) to 24.1 within 1 MB. Rather than competing with GPU-scale parsers, we map the accuracy memory trade-off across representations, bit-widths, capacities, and post-processing strategies for embedded vision systems.

Multi-view computer vision pipelines typically rely on accurate sparse keypoints and robust descriptors. While incorporating line features has shown clear benefits for matching and pose estimation, existing point-line approaches remain inefficient: they detect points and lines separately, use increasingly heavy networks, and depend on CPU-bound heuristics that hinder real-time performance. We introduce a Unified Efficient Points and Lines (UPAL) feature extractor that jointly extracts keypoints, line segments, and feature descriptors within a single lightweight architecture. A shared backbone provides common representations that feed different branches for point and line features. Line segments are recovered through an accelerated post-processing stage, an enhanced and highly efficient variant of the LSD algorithm. UPAL matches or exceeds state-ofthe-art performance in both point and line applications while significantly reducing computational cost, achieving, for instance, a 4x speedup and 10x smaller memory footprint over the ALIKED + DeepLSD pipeline. Code is publicly available at https://github.com/francois141/upal.