DVA-Neurons: Design and Verification of Adaptive LIF Neurons: From Single-Neuron Dynamics to Multi-Neuron Spiking Networks

Thanh Pham; Riadul Islam

cs.AISep 19, 2026

DVA-Neurons: Design and Verification of Adaptive LIF Neurons: From Single-Neuron Dynamics to Multi-Neuron Spiking Networks

Authors: Thanh Pham, Riadul Islam

Organizations: Department of Computer Science and Electrical Engineering, University of Maryland, Baltimore County, MD 21250, United States

Abstract

Spiking Neural Networks (SNNs) offer a promising path toward ultra-low-power artificial intelligence inference by emulating the event-driven computation of biological neurons. However, two challenges limit their practical deployment. First, fixed-parameter Leaky Integrate-and-Fire (LIF) neurons lack the adaptation mechanisms observed in biology, where neurons modulate their excitability based on firing history. Second, scaling from single neurons to multi-neuron networks introduces challenges in synaptic weight distribution and inter-neuron spike routing that are absent in isolated designs. This paper addresses both issues through the extension, verification, and physical implementation of adaptive LIF neurons at three architectural scales. This work contributes: a 2nd-order neuron with two-stage synaptic filtering for richer temporal dynamics; a fully-connected 6-neuron spiking network with configurable weights (100 to 5) demonstrating weight-based inter-neuron communication; and a direct verification methodology enabling per-cycle observation of all internal states. All designs were synthesized targeting Selected Area Electron Diffraction (SAED) 14 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology at 1 GHz and verified with Cocotb-based Python testbenches under pulsed current stimuli (amplitude 80, ISI=3). The results show that adaptation effectively modulates firing: 31% suppression in the 2nd-order neuron (25 vs.\ 36 spikes) and 31% reduction in postsynaptic firing in the network (18 vs.\ 26 spikes). Physically, the 2nd-order neuron costs 1.77x more area and 1.52x more power than the 1st-order baseline, while the 6-neuron network demonstrates near-linear scaling (5.7x area, 5.3x power). Seven verification bugs spanning testbench connectivity, fixed-point overflow, and Verilog expression-width semantics are documented.

Figures & tables

Figure 1: Block diagram of the 2nd-order LIF neuron showing the two-stage pipeline: synaptic filtering ( $\alpha$ ) followed by membrane integration ( $\beta$ ), with adaptive threshold and adaptive beta feedback paths.

Figure 2: Adaptive threshold calculation. On spike: $threshold\leftarrow threshold\times 295/256$ (increase, clamped to 220). On non-spike: $threshold\leftarrow threshold\times 250/256$ (decay, clamped to 32).

Figure 3: Adaptive beta calculation. On spike: $\beta\leftarrow\beta\times 250/256$ (more leak, clamped to 128). On non-spike: $\beta\leftarrow\beta\times 295/256$ (less leak, clamped to 220).

Architecture/Work	Dynamic Adaptation Features	Core Area/ Neuron( $\mu\text{m}^{2}$ )	Dynamic Power/ Neuron( $\mu\text{W}$ )
IBM TrueNorth	None (Fixed LIF)	$\sim 365$	$0.02$
Intel Loihi	Programmable Threshold & STDP	$\sim 390$ (amortized)	$\sim 20\text{--}50$
TT05 LIF Baseline	Adaptive Threshold & $\beta$	N/A	N/A
This 1st-Order	Adaptive Threshold & $\beta$	303.56	$\mathbf{83.60}$
This 2nd-Order	2nd-Order Synaptic + Adapt Thresh/ $\beta$	393.78	$\mathbf{127.00}$
This 6-Neuron Net	Fully Connected + Multi-Neuron Adapt	374.02 (avg/neuron)	111.50 (avg/neuron)

Table 1: Quantitative Comparison of Digital Neuron Architectures and Neuromorphic Processors

Test	Spikes	ISI	Observation
T1: Both ON	14	5 $\rightarrow$ 6 growing	Active adaptation
T2: Thresh only	13	flat 6, dips to 3–4	Threshold dominates
T3: Beta only	12	constant 6	Same as baseline
T4: Both OFF	12	constant 6	Pure LIF reference
T5: Rate coding	5/7/7	S/M/F	Saturates at ISI=2

Table 2: 1st-Order LIF Neuron Results (25 pulses, amplitude 80)

Test	Spikes	ISI	Observation
T1: Both ON	25	2 $\rightarrow$ 3 stable	Adapt suppresses 31% vs. T4
T2: Thresh only	25	same as T1	Threshold dominates adapt
T3: Beta only	36	2 $\rightarrow$ 3 $\rightarrow$ 2 steady	Same as baseline
T4: Both OFF	36	2 $\rightarrow$ 3 $\rightarrow$ 2 steady	Pure LIF reference
T5: Rate coding	8/10/11	S/M/F	Higher rate, more spikes

Table 3: 2nd-Order LIF Neuron Results (25 pulses, amplitude 80)

Test	Metric	Value	Observation
T1: One-to-one	N0/N1 spikes	17/17	Perfect 1:1 coupling
T2: Fan-out	L1 syn values	80/24/12/8/4	Weight-dependent
T3: Strong vs weak	N1/N5 spikes	17/0	Weight-dependent
T4: Rate coding	N2 (S/M/F)	0/10/12	Rate-dependent
T5: Adaptation	ON/OFF N1 spikes	18/26	31% suppression

Table 4: Network Results (pulsed N0 drive, amplitude 80)

Amplitude	ISI=2	ISI=3	ISI=4	ISI=5	ISI=6	Observation
Amp = 40	7/2	8/0	4/0	0/0	0/0	Sub-threshold dissipation
Amp = 60	9/5	9/0	9/0	9/0	9/0	High leak dissipation
Amp = 80	10/5	13/4	14/5	10/0	10/0	Moderate temporal summation
Amp = 100	10/6	14/8	18/10	19/8	19/0	Multi-spike bursting
Amp = 120	10/6	15/8	19/11	19/8	19/8	Inverse rate-coding saturation

Table 5: Parameter Sweep Firing Response Grid (

N_{0}/N_{2}

Spikes)

Metric	1st-Order	2nd-Order	Network
Sequential cells	24	32	186
Combinational cells	442	548	3,271
Total cells	466	580	3,457
Buf/Inv cells	43	53	283
Cell area ( $\mu m^{2}$ )	184.97	237.76	1,353.36
Interconnect area ( $\mu m^{2}$ )	135.44	328.26	1,950.60

Table 6: Design Compiler Cell Count and Area (SAED 14 nm, 1 GHz)

Metric	1st-Order	2nd-Order	Network
DC Synthesis Stage (Pre-CTS / Ideal Clock)
DC Max setup slack (ns)	0.00	0.00	0.00
DC Critical path delay (ns)	0.89	0.88	0.89
DC Min hold slack (ns)	$-0.18$	$-0.06$	$-0.07$
Startpoint	beta_reg_1_	syn_reg_0_	n0_mem_reg_1_
Endpoint	state_reg_7_	mem_reg_5_	N1_mem_reg_0_

Table 7: Synthesis (DC) vs. Physical Implementation (ICC2 Post-CTS) Timing Comparison (1 GHz Constraint)

Power Group	1st-Order	2nd-Order	Network
Clock network ( $\mu W$ )	16.14 (24.3%)	18.49 (23.5%)	124.28 (31.5%)
Registers ( $\mu W$ )	13.39 (20.2%)	14.66 (18.7%)	58.89 (14.9%)
Combinational ( $\mu W$ )	36.91 (55.6%)	45.46 (57.8%)	212.02 (53.7%)
Total dynamic ( $\mu W$ )	66.38	78.53	394.74
Leakage (nW)	58.90	81.43	451.24

Table 8: Design Compiler Power Estimates (0.8V, 25°C, default activity)

Metric	1st-Order	2nd-Order	Network
Core area ( $\mu m^{2}$ )	303.56	393.78	2,244.15
Chip area ( $\mu m^{2}$ )	1,454.88	1,649.66	4,687.51
Core utilization	66.6%	63.6%	65.0%
Site rows	43	49	117

Table 9: ICC2 Physical Design Summary (SAED 14 nm, 0.8V SS)

Metric	1st-Order	2nd-Order	Network
Clock sinks	24	32	186
CTS levels	2	2	3
Repeaters inserted	2	1	2
Repeater area ( $\mu m^{2}$ )	0.62	0.49	1.47
Total wire length ( $\mu m$ )	61.68	86.26	440.69
Max latency (ns)	0.03	0.04	0.08

Table 10: ICC2 Clock Tree Synthesis Results

Power Group	1st-Order	2nd-Order	Network
Clock network ( $\mu W$ )	23.80 (28.5%)	30.60 (24.1%)	197.00 (29.4%)
Registers ( $\mu W$ )	17.90 (21.4%)	34.20 (27.0%)	131.00 (19.5%)
Combinational ( $\mu W$ )	41.90 (50.1%)	61.90 (48.8%)	342.00 (51.1%)
Total dynamic ( $\mu W$ )	83.60	127.00	669.00
Leakage (nW)	66.10	85.60	492.00

Table 11: ICC2 Post-Layout Power (0.8V, 25°C, SS Corner)

Metric	1st-Order	2nd-Order	Network
DC cells	466	580	3,457
DC total area ( $\mu m^{2}$ )	320.41	566.02	3,303.95
ICC2 core area ( $\mu m^{2}$ )	303.56	393.78	2,244.15
ICC2 chip area ( $\mu m^{2}$ )	1,454.88	1,649.66	4,687.51
DC dynamic power ( $\mu W$ )	66.38	78.53	394.74
ICC2 dynamic power ( $\mu W$ )	83.60	127.00	669.00

Table 12: Physical Design Comparison Across All Three Architectures

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