The pervasive deployment of Deep Neural Networks (DNNs) across the computing spectrum has brought growing attention to energy efficiency, alongside raw performance. While voltage scaling is a potent knob for power reduction, its application in next-generation nodes is hampered by severe throughput degradation and susceptibility to process variation. This work aims to address these energy-reliability trade-offs by introducing a hardware-software co-design methodology, based on the observation that timing-robust bit ranges within the accumulator of a systolic array vary significantly across different voltage-frequency operating points. At the software level, we propose an Accumulation-Aware Training approach that incorporates this information as a first-order optimization constraint during training. By integrating mixed-precision quantization with unstructured pruning, we effectively constrain the model's weight distribution to avoid activating the hardware's sensitized high-rank carry chains. At the architectural level, we complement this with selective MSB-masking and fine-grained clock-gating to minimize unnecessary dynamic switching activity. Furthermore, we employ a layer-wise Dynamic Frequency Scaling strategy to further adapt to the accumulator's reduced dynamic range, based on the numerical sensitivity of each layer. We experimentally evaluate the proposed solution on a deep scaled 2nm technology node and demonstrate that, when operating at a low-voltage frontier, our co-optimized post-layout architecture delivers substantial energy and energy-delay product gains of 39% and 23% respectively, relative to the nominal voltage implementation, while maintaining accuracy degradation within 1%.
Figures & tables
Figure 1. Overview of the examined output stationary systolic array, along with the considered scaled Vdd region. Overview of Baseline Architecture
Figure 2. Delay Distribution in major components of the Systolic array design at different Vdd corners and under the effects of Threshold Voltage Variation. Delay/Power Corner Analysis
Figure 3. Comparative analysis of the Systolic Array across different supply & threshold voltage conditions. Delays per component in the design
Figure 4. End-to-end DNN evaluation methodology for examined operating conditions and extracted error distributions. Gate-Level Error Evaluation Methodology
Figure 5. Error Distribution of the accumulator within MAC units at 0.5V as we scale the frequency, along with the impact of threshold voltage variability on the error probability. Error Distribution of the MAC accumulator.
Freq.
Safe
Power
Norm. EDP
Efficiency
(GHz)
Bits
(mW)
(vs. 0.7V )
(TOPS/W)
1.0
24
90
1.45
22.7
1.2
22
109
1.24
22.5
1.4
19
117
0.99
24.5
1.6
17
124
0.80
26.4
1.8
14
125
0.63
29.4
Table 1. Accumulator Reliability and Efficiency Metrics ( VDD=0.5\text{,}\mathrm{V}$$ ) after MSB masking and clock-gating
Figure 6. Accumulation-Aware Exploration Flow. Iterative EDP optimization through layer-wise selection of weight and accumulator bit-widths, guided by configurations in Table 1 . Fine-Tuning Methodology
Figure 7. Evaluation of hardware-aware optimization stages under 1% loss accuracy constraint. The top row depicts the distribution of the minimum required accumulator bit-width ( Pmin ), overlaid with normalized hardware metrics (Latency, Energy, and EDP) relative to the (INT8, 0.7V @ 2GHz) baseline. The bottom row illustrates layer-wise breakdowns of the final Pmin assignments, while the bar colors denote the quantization precision assigned to each layer, highlighting their correlation. Methodology Results
Work
Node
VDD Range
Benchmark †
Energy Gains
X-TPU ( Senobari et al., 2024 )
15nm
0.5V - 0.8V
ResNet-50 (C)
35.0%
JETCAS ’19 ‡ ( Shin et al., 2019 )
65nm
0.73V - 1.08V
ResNet-50 (I)
34.0%
X-NVDLA ( Afzali-Kusha and Pedram, 2022 )
15nm
0.4V - 0.8V
ResNet-50 (I)
41.5%
GAVINA ( Fornt et al., 2025 )
12nm
0.35V - 0.55V
ResNet-18 (C)
20.0%
ThunderVolt ‡ ( Su et al., 2023 )
45nm
0.65 - 1.0 §
AlexNet (I)
45.0%
This Work
2nm
0.5V
ResNet-18 (C) ResNet-50 (I)
41% / 43%*
Table 2. Comparison with State-of-the-Art Voltage-Scaling DNN Accelerators under 1% accuracy constraint.
Deploying deep neural networks (DNNs) on power-sensitive edge devices presents a formidable challenge. While Dynamic Voltage and Frequency Scaling (DVFS) is widely employed for energy optimization, traditional model-level scaling is often too coarse to capture intra-inference variations, whereas fine-grained operator-level scaling suffers from prohibitive performance degradation due to significant hardware switching latency. This paper presents SparseDVFS, a fine-grained, sparse-aware DVFS framework designed for energy-efficient edge inference. Our key insight is that operator sparsity is a primary metric for hardware frequency modulation. By distinguishing between compute-bound dense operators and memory-bound sparse operators, the system can apply specialized frequency triplets to maximize energy efficiency. To overcome switching overheads and component interference, SparseDVFS incorporates three key innovations: (1) an offline modeler that established a deterministic mapping between operator sparsity and optimal frequency triplets (CPU/GPU/EMC) via white-box timeline analysis; (2) a runtime graph partitioner that utilizes a greedy merging heuristic to aggregate operators into super-blocks, balancing scaling granularity and DVFS switching latency through a latency amortization constraint; and (3) a unified co-governor that employs a frequency unified scaling engine (FUSE) and a look-ahead instruction queue to eliminate antagonistic effects between independent controllers and hide hardware transition latencies. Extensive evaluations show that SparseDVFS achieves an average 78.17% energy efficiency gain over state-of-the-art solutions while maintaining a superior 14% cost-gain ratio.
Ziyang Zhang, Zheshun Wu, Jie Liu +1
Politecnico di Milano, Milan, Italy · Harbin Institute of Technology, Shenzhen, China
The deployment of Early-Exiting Neural Networks (EENNs) on edge accelerators requires optimizing not only the network architecture but also its hardware deployment. Exit configuration, quantization, and hardware workload mapping interact in non-trivial ways, influencing memory traffic, accelerator utilization, and ultimately the energy-latency trade-off. This work presents a hardware-aware co-design framework for EENNs that jointly optimizes exit configuration, quantization-aware training, and multi-core hardware mapping within a unified NAS process. Leveraging analytical design space exploration, the framework identifies efficient workload mappings for each candidate architecture while providing accurate latency and energy estimates during the search. We further formulate EENN deployment as a constrained multi-objective optimization problem balancing predictive accuracy, energy-latency product, exit overhead, and dynamic inference efficiency. Experimental results on CIFAR-10 demonstrate that the proposed framework achieves over a 50% reduction in energy-latency product compared with static baselines under 8-bit quantization. These results demonstrate that jointly optimizing architecture and deployment is essential for realizing the full efficiency potential of dynamic inference on heterogeneous edge accelerators.
Alaa Zniber, Arne Symons, Ouassim Karrakchou +2
TICLab, International University of Rabat, Morocco · MICAS, KU Leuven, Belgium
Deploying deep neural networks on resource-constrained 6G edge devices demands aggressive compression with minimal accuracy loss. Quantization-Aware Training (QAT) has emerged as a leading compression approach; however, existing mixed-precision methods typically operate at coarse layer- or channel-level granularity. These methods often rely on heuristic or search-based bit-allocation strategies, which may overlook fine-grained variability at the neuron level. We propose Neuron-Level Mixed-Precision QAT (NMP-QAT), where each neuron independently learns its own discrete precision during training. Starting from low-bit precision, NMP-QAT expands bit-width only when training signals demand it, via differentiable surrogates and straight-through estimators, while preserving a fully discrete inference graph. This adaptability extends to both weights and activations, reducing memory movement. Evaluated on telecom and non-telecom datasets across MLP and tabular foundation model architectures, NMP-QAT achieves superior compression-accuracy trade-offs over mixed-precision QAT baselines, making it well-suited for Green AI deployments at the network edge.
Ayush K. Varshney, Konstantinos Vandikas, Šarūnas Girdzijauskas +2
Ericsson Research, Ericsson AB, Stockholm, Sweden · KTH Royal Institute of Technology, Stockholm, Sweden · RISE Research Institutes of Sweden, Stockholm, Sweden