State-Dependent Memristor Dynamics for Device-Informed Spike-Timing-Dependent Plasticity in Spiking Neural Networks

Samiur Rahman Khan; Saifur Rahman Sabuj

cs.NEOct 28, 2026

State-Dependent Memristor Dynamics for Device-Informed Spike-Timing-Dependent Plasticity in Spiking Neural Networks

Authors: Samiur Rahman Khan, Saifur Rahman Sabuj

Organizations: University of Cincinnati, Cincinnati, OH, USA · BRAC University, Dhaka, Bangladesh

Abstract

This work investigates device-informed spike-timing-dependent plasticity (STDP) in spiking neural networks using a literature-derived threshold-memristor model. Local STDP commands determine programming polarity and a programming coordinate for state-dependent conductance updates in the first fully connected layer, while a backpropagation-trained readout performs classification. HSPICE simulations characterize thresholded, polarity- and state-dependent device dynamics and differential crossbar multiply-accumulate behavior. Experiments on MNIST and Fashion-MNIST compare the hybrid learning rule with direct clipped STDP and evaluate programming asymmetry, device-parameter variation, write noise, stuck-at faults, and input corruption. The hybrid model achieved 95.15% accuracy on MNIST and 85.92% on Fashion-MNIST. In a separate seed-matched comparison, it reached 95.02% and 84.79%, versus 92.33% and 83.25% for direct clipped STDP. Potentiation-dominant asymmetry reduced input-dependent feature selectivity, and endpoint faults introduced during training were less damaging than faults introduced after training. The network-level mapping is a reduced-order, validation-selected abstraction rather than a pulse-accurate physical programming implementation. These results quantify how state-dependent memristor dynamics shape local-STDP learning and its sensitivity to hardware nonidealities.

Figures & tables

Parameter	Value
$R_{\mathrm{ON}}$	$10~\Omega$
$R_{\mathrm{OFF}}$	$420~\Omega$
$V_{\mathrm{TH}}^{-}$	$-0.19~\mathrm{V}$
$V_{\mathrm{TH}}^{+}$	$0.37~\mathrm{V}$
$D$	$3~\mathrm{nm}$
$\mu_{v}$	$1.6\times 10^{-12}~\mathrm{m^{2}\,s^{-1}\,\Omega^{-1}}$

TABLE I: Parameters of the adopted threshold-memristor model [ 26 ] .

Fig. 1: HSPICE characterization of the adopted threshold-memristor model: (a) transient memristance response under alternating $\pm 1.0~\mathrm{V}$ , $110~\mu\mathrm{s}$ programming pulses; (b) current–voltage response under 100-Hz sinusoidal excitation with peak voltages from $0.15$ to $1.00~\mathrm{V}$ ; (c) average normalized state-update rate $\Delta w_{\mathrm{norm}}/\Delta t$ over a 100-ns pulse versus applied voltage for $w_{\mathrm{norm},0}=0.2$ , $0.5$ , and $0.8$ , on a symmetric logarithmic vertical axis with the threshold dead zone shaded; (d) SET ( $+0.6~\mathrm{V}$ ) and RESET ( $-0.6~\mathrm{V}$ ) transition times over normalized-state intervals; (e) corresponding $T_{\mathrm{SET}}/T_{\mathrm{RESET}}$ ratios; and (f) relative conductance change versus programming-pulse width for $w_{\mathrm{norm},0}=0.2$ , $0.5$ , and $0.8$ under $\pm 0.60~\mathrm{V}$ pulses.

Fig. 2: Reduced differential-crossbar HSPICE analysis. (a) Differential conductance mapping and static signed-MAC configuration, shown as a three-input, three-class excerpt of the $64\times 10$ logical classifier, with each signed weight represented by the differential pair $G_{ij}^{+}$ and $G_{ij}^{-}$ . (b) Interconnect model used for the resistance sweep, shown as a two-input, one-class excerpt: input rows are driven through $R_{\mathrm{wire}}/2$ , row and column segments include $R_{\mathrm{wire}}$ , and each physical output column ( $G_{j}^{+}$ and $G_{j}^{-}$ ) connects to ideal current sensing through $R_{\mathrm{sense}}$ , with $R_{\mathrm{sense}}=2~\Omega$ (fixed) or $2R_{\mathrm{wire}}$ (proportional).

Fig. 3: Qualitative timing comparison between the HSPICE paired-pulse response and the trace-based STDP timing response, shown versus relative timing $\Delta t=t_{\rm post}-t_{\rm pre}$ in $\mu\mathrm{s}$ .

Fig. 4: Numerical consistency between the explicit single-step update in Eq. ( 16 ) and the finer-grained evaluation of the same reduced-order mapping across 462 conditions. The dashed line denotes equality.

Dataset	Synapses	Updated/batch	Active fraction	Batch range
MNIST	802,816	$423{,}987\pm 10{,}291$	$52.81\pm 1.28\%$	367,678–457,198
Fashion-MNIST	802,816	$710{,}470\pm 20{,}156$	$88.50\pm 2.51\%$	577,363–755,556

TABLE II: Realized fc1 batch-aggregated update activity for the final 1024-hidden-neuron, batch-128 configurations retrained on the complete training sets. A synapse is counted as active when

\overline{\Delta W}_{{\rm raw},ij}^{b}\neq 0

. Values are mean

\pm

standard deviation over mini-batches pooled across five independent seeds.

Parameter	MNIST	Fashion-MNIST
Hidden neurons	1024	1024
Batch size	128	128
Training epochs	100	100
Simulation timesteps, $T$	25	15
STDP trace constant, $\tau_{\mathrm{pre}}=\tau_{\mathrm{post}}$ (timesteps)	1.2474	1.9955
Balanced STDP coefficient, $A_{+}=A_{-}=A_{0}$	$4.860\times 10^{-4}$	$1.505\times 10^{-4}$

TABLE III: Network and learning parameters for the final hybrid SNN configurations. Dataset-dependent parameters were selected using validation data.

Fig. 5: Representative confusion matrices for the 1024-hidden-neuron, batch-128 hybrid SNN: (a) MNIST evaluated on the 8,920-image test set containing 892 images per class and (b) Fashion-MNIST evaluated on its native 10,000-image test set containing 1,000 images per class.

Dataset	Hidden	Batch	Hybrid	Ideal BP	Memristor BP	Memristor BP + norm.
Fashion-MNIST	512	64	$83.88\pm 0.29$	$87.68\pm 0.55$	$83.41\pm 0.92$	$66.04\pm 6.81$
Fashion-MNIST	512	128	$84.41\pm 0.14$	$87.99\pm 0.24$	$83.85\pm 1.42$	$76.91\pm 1.85$
Fashion-MNIST	1024	64	$85.34\pm 0.17$	$88.32\pm 0.19$	$82.36\pm 3.41$	$58.78\pm 6.48$
Fashion-MNIST	1024	128	$85.92\pm 0.23$	$88.37\pm 0.33$	$84.38\pm 1.16$	$81.51\pm 2.51$
MNIST	512	64	$89.94\pm 0.49$	$97.79\pm 0.32$	$94.37\pm 0.31$	$67.11\pm 17.35$
MNIST	512	128	$93.07\pm 0.21$	$97.93\pm 0.14$	$94.70\pm 0.29$	$87.49\pm 6.28$

TABLE IV: Classification test accuracy under four fc1 learning conditions: device-informed STDP (Hybrid), end-to-end backpropagation with signed, unconstrained weights (Ideal BP), and backpropagation-driven programming of the threshold-memristor states without and with epoch-wise column normalization (Memristor BP and Memristor BP + norm.). Values are mean

\pm

standard deviation over five seeds. Hybrid values are the nominal Hybrid population. The comparison with Ideal STDP and the paired statistical comparisons at the 1024-hidden-neuron, batch-128 configuration are reported in the text.

Condition	MNIST (%)	Fashion-MNIST (%)
Hybrid (full response factor)	$95.15\pm 0.17$	$85.92\pm 0.23$
Constant rate	$94.98\pm 0.26$	$85.63\pm 0.09$

TABLE V: Ablation of the programming-rate response factor for the 1024-hidden-neuron, batch-128 configuration. The constant-rate condition removes the resistance, current, and boundary-window dependence together. Values are final test accuracy in percent, reported as mean

\pm

standard deviation over five matched seeds.

Fig. 6: Test accuracy versus STDP coefficient-asymmetry magnitude $\rho$ for the $A_{+}$ - and $A_{-}$ -dominant conditions of Eq. ( 21 ): (a) MNIST and (b) Fashion-MNIST. Error bars denote one standard deviation over three seeds.

Fig. 7: Final fc1 effective-weight distributions under controlled STDP coefficient-asymmetry magnitude $\rho$ . Each panel shows the mean fraction of fc1 synapses in each bin of the conductance-derived forward weight $W_{\mathrm{fc1}}$ of Eq. ( 17 ) over three seeds for $\rho=1.0$ , $1.5$ , $3.0$ , and $5.0$ : (a) MNIST $A_{+}$ -dominant, (b) MNIST $A_{-}$ -dominant, (c) Fashion-MNIST $A_{+}$ -dominant, and (d) Fashion-MNIST $A_{-}$ -dominant. The vertical axis is logarithmic; empty bins are not shown.

Fig. 8: Test accuracy under independent pixel-intensity inversion ( $x_{i}\rightarrow 1-x_{i}$ ) at $p_{\mathrm{flip}}=\{0,6.67,13.33,20,30\}\%$ . Error bars denote one standard deviation over five independently trained models.

Fig. 9: Classification accuracy under (a) endpoint stuck-at faults present throughout training and evaluation and (b) device-parameter variation in $R_{\mathrm{ON}}$ , $R_{\mathrm{OFF}}$ , $V_{\mathrm{TH}}^{+}$ , and $V_{\mathrm{TH}}^{-}$ . Variation levels denote the relative standard deviation of the Gaussian perturbation before clipping. Error bars denote one standard deviation over five seeds.

Experiment	Condition	MNIST		Fashion-MNIST		Timing
		Accuracy (%)	Change (pp)	Accuracy (%)	Change (pp)
Pixel-flip input noise	$p_{\mathrm{flip}}=0$	$95.21\pm 0.17$	—	$85.86\pm 0.20$	—	After training
Pixel-flip input noise	$p_{\mathrm{flip}}=6.67\%$	$61.71\pm 0.43$	$-33.50$	$73.09\pm 0.32$	$-12.77$	After training
Pixel-flip input noise	$p_{\mathrm{flip}}=13.33\%$	$39.10\pm 0.41$	$-56.11$	$56.26\pm 0.68$	$-29.60$	After training
Pixel-flip input noise	$p_{\mathrm{flip}}=20\%$	$26.61\pm 0.73$	$-68.60$	$41.17\pm 0.82$	$-44.69$	After training
Pixel-flip input noise	$p_{\mathrm{flip}}=30\%$	$16.84\pm 0.35$	$-78.37$	$24.51\pm 0.49$	$-61.35$	After training

TABLE VI: Summary of robustness experiments. Each clean reference is the zero-perturbation result of the corresponding experiment; the two endpoint-fault references are the nominal Hybrid population of Table IV . Values are mean

\pm

standard deviation in percent over five independently trained models (three for write noise). Post-training endpoint faults were injected into the final-epoch clean-trained models of the training-time fault experiment without retraining. Changes are relative to the clean reference within each experiment family.

Spike-Timing-Dependent Plasticity

Spike-timing-dependent plasticity (STDP) changes synaptic strength according to the relative timing of pre- and postsynaptic spikes.

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Sep 14, 2026

A Memristive Synapse for Online STDP Learning and Inference in SNNs

This work presents a fully analog memristive synaptic circuit for online spike-timing-dependent plasticity (STDP) learning in spiking neural networks (SNNs). The proposed synapse integrates a local STDP circuit generating gradual timing-dependent conductance updates directly from pre- and post-synaptic spikes. Learning occurs during normal network operation without requiring external digital control or explicit STDP waveform synthesis. Post-layout simulations of the memristive synapse implemented in a 130 nm CMOS technology show spike-timing-dependent conductance adaptation during SNN operation. A 2x2 SNN simulation further illustrates online neuron specialization through unsupervised learning.

Elia Mateu-Barriendos, Álvaro Gómez-Pau, Daniel Arumí +2

Universitat Polit`ecnica de Catalunya - BarcelonaTech (UPC)

Spiking Neural Networks Spike-Timing-Dependent Plasticity Neuromorphic Computing Online Learning

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Jul 28, 2025

Efficient Memristive Spiking Neural Networks Architecture with Supervised In-Situ STDP Method

Memristor-based Spiking Neural Networks (SNNs) with temporal spike encoding enable ultra-low-energy computation, making them ideal for battery-powered intelligent devices. This paper presents a circuit-level memristive spiking neural network (SNN) architecture trained using a proposed novel supervised in-situ learning algorithm inspired by spike-timing-dependent plasticity (STDP). The proposed architecture efficiently implements lateral inhibition and the refractory period, eliminating the need for external microcontrollers or ancillary control hardware. All synapses of the winning neurons are updated in parallel, enhancing training efficiency. The modular design ensures scalability with respect to input data dimensions and output class count. The SNN is evaluated in LTspice for pattern recognition (using 5x3 binary images) and classification tasks using the Iris and Breast Cancer Wisconsin (BCW) datasets. During testing, the system achieved perfect pattern recognition and high classification accuracies of 99.11% (Iris) and 97.9% (BCW). Additionally, it has demonstrated robustness, maintaining an average recognition rate of 93.4% under 20% input noise. The impact of stuck-at-conductance faults and memristor device variations was also analyzed.

Santlal Prajapati, Susmita Sur-Kolay, Soumyadeep Dutta

Advanced Computing and Microelectronics Unit, Indian Statistical Institute, Kolkata 700108, India · Balasore Alloys Limited, Balgopalpur, Odisha 756020, India

Efficient Neural Network Inference Spiking Neural Networks Neuromorphic Computing

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Jun 4, 2026

ITP-STDP: A Hardware-Efficient Intrinsic-Timing Power-of-Two Synaptic Learning Engine for On-Chip SNNs

Spiking neural networks (SNNs) have the potential to emerge as the third generation of neural networks and have attracted increasing attention across a wide range of applications. However, the large number of synaptic connections in SNNs leads to intensive weight-update computation by on-chip learning algorithms during training, resulting in substantial hardware resource utilization and energy consumption. Among existing SNN learning algorithms, spike-timing-dependent plasticity (STDP) is one of the most extensively studied and widely adopted, serving as a fundamental learning component in SNNs. To address the hardware and energy overheads associated with SNN training, this paper presents intrinsic-timing power-of-two STDP (ITP-STDP) and its corresponding prototype learning engine hardware architecture. The proposed design is evaluated through a dedicated mean-field synaptic drift model for dynamical analysis and further validated across SNN networks of different scales and datasets. It is further implemented on both ASIC and FPGA platforms and compared with state-of-the-art approaches, including the original STDP and more complex STDP variants. The results demonstrate superior energy efficiency, higher operating speed, and substantially lower hardware resource utilization, as the proposed design eliminates most of the computational overhead of STDP through both algorithmic and hardware-level optimizations. On the FPGA platform, the proposed design improves energy efficiency by 4.5

\times

to 219.8

\times

over the compared designs. On the ASIC platform, the proposed design achieves a 4.8

\times

to 22.01

\times

speedup while consuming only 1.2% to 3.3% of the area required by prior works.

Haihang Xia, Xinyu Zhao, Xuecheng Wang +5

School of Electrical and Electronic Engineering, The University of Shefﬁeld, S1 3JD Shefﬁeld, U.K. · Donghai Laboratory, Zhoushan 316021, China · Engineering Research Center of Oceanic Sensing Technologyand Equipment, Ministry of Education, Zhoushan 316021, China +1

Spiking Neural Networks Spike-Timing-Dependent Plasticity Neuromorphic Computing FPGA-Based Neural Network Acceleration

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Abstract

Spike-Timing-Dependent Plasticity

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