Chimera: Neuro-Symbolic Attention Primitives for Trustworthy Dataplane Intelligence

Rong Fu; Xiaowen Ma; Kun Liu; Wangyu Wu; Ziyu Kong; Jia Yee Tan; Tailong Luo; Xianda Li

cs.NIFeb 13, 2026

Chimera: Neuro-Symbolic Attention Primitives for Trustworthy Dataplane Intelligence

Authors: Rong Fu, Xiaowen Ma, Kun Liu, Wangyu Wu, Ziyu Kong, Jia Yee Tan, Tailong Luo, Xianda Li,

Organizations: Independent Researcher

Abstract

Deploying expressive learning models directly on programmable dataplanes promises line-rate, low-latency traffic analysis but remains hindered by strict hardware constraints and the need for predictable, auditable behavior. Chimera introduces a principled framework that maps attention-oriented neural computations and symbolic constraints onto dataplane primitives, enabling trustworthy inference within the match-action pipeline. Chimera combines a kernelized, linearized attention approximation with a two-layer key-selection hierarchy and a cascade fusion mechanism that enforces hard symbolic guarantees while preserving neural expressivity. The design includes a hardware-aware mapping protocol and a two-timescale update scheme that together permit stable, line-rate operation under realistic dataplane budgets. The paper presents the Chimera architecture, a hardware mapping strategy, and empirical evidence showing that neuro-symbolic attention primitives can achieve high-fidelity inference within the resource envelope of commodity programmable switches.

Figures & tables

Figure 1: Overview of the Chimera architecture for trustworthy dataplane intelligence. The pipeline executes within a P4 Programmable Switch across three primary stages: Partition , where the incoming Packet Stream is segmented into discrete units $X_{1},\dots,X_{k}$ ; Map , which bifurcates into a Neural Path ( $\phi$ ) for computing Linearized Attention via high-dimensional feature maps and a Symbolic Path ( $\mathcal{R}$ ) that executes Rule Matching against hardware-resident Symbolic Constraints ; and SumReduce , which aggregates partial results. These paths converge in the Cascade Fusion engine, which applies a Hard Veto / Soft Blend logic to ensure safety guarantees while maintaining neural expressivity. The final output is a Trustworthy Score representing a verified, line-rate inference result.

Figure 2: Two-layer key selection hierarchy and memory efficiency analysis. (Left) The architectural flow of Chimera: combining temporal locality in the SRAM-based Local Layer with structural prior knowledge in the TCAM-indexed Static Layer to perform sparse key selection. (Right) Comparative memory footprint showing Chimera’s significant reduction in per-flow state compared to dense and linearized baselines.

Method	Input Scale (b)	Model Size (Kb)	PeerRush [ 44 ]			CICIOT [ 45 ]			ISCXVPN [ 46 ]
			PR	RC	F1	PR	RC	F1	PR	RC	F1
Leo (Decision Tree) [ 47 ]	128	-	0.8720	0.8776	0.8728	0.7910	0.8072	0.7848	0.7338	0.7797	0.7475
N3IC (binary MLP) [ 48 ]	128	24.4	0.8217	0.8308	0.8241	0.7855	0.7877	0.7745	0.6688	0.6521	0.6388
MLP-B	128	34.3	0.8823	0.8826	0.8823	0.8555	0.8615	0.8581	0.7676	0.7552	0.7574
BoS (binary RNN) [ 11 ]	18	25.6	0.8677	0.8696	0.8678	0.8311	0.8253	0.8276	0.7033	0.7089	0.6907
RNN-B [ 11 ]	128	10.9	0.9083	0.9100	0.9090	0.8707	0.8708	0.8707	0.7848	0.7658	0.7617

Table 1: Comparison of classification accuracy across different methods. The table spans two columns.

Models	Stateful bits/flow	SRAM	TCAM	Bus
Leo [ 47 ]	80	2.44%	21.67%	3.55%
BoS [ 11 ]	72	2.81%	0%	0.74%
MLP-B	80	7.75%	12.92%	29.45%
RNN-B [ 11 ]	240	7.38%	23.33%	33.36%
CNN-B [ 49 ]	72	5.56%	7.08%	13.16%
CNN-M [ 49 ]	72	3.50%	6.67%	3.98%

Table 2: Hardware resource utilization for different methods. The table is formatted for a single column.

Figure 3: Transformation from standard attention to dataplane-native primitives. (a) Architectural comparison between infeasible exact attention and Chimera’s linearized formulation. (b) Temporal unfolding of incremental state updates mapped to stateful ALU operations.

Figure 4: Pareto frontier: CICIOT F1 versus per-flow state bits. Chimera is highlighted as Pareto-optimal, providing higher accuracy with lower per-flow state than competing dataplane models.

Figure 5: Input-scale sensitivity: CICIOT F1 as a function of input window size. Chimera scales sub-linearly in state while benefiting from wider contexts.

Figure 6: Throughput comparison (Gbps). Chimera running on a Tofino target achieves line-rate throughput, significantly exceeding CPU/GPU implementations.

Figure 7: Latency distributions (log-scale boxplots approximating median and P99). Chimera attains microsecond-level median and tail latencies with minimal jitter.

Figure 8: ROC curves for unsupervised anomaly detection on PeerRush, CICIOT and ISCXVPN. The AutoEncoder implemented with Chimera primitives produces high AUC values, indicating robust separation of anomalous traffic.

Figure 9: Hyperparameter sensitivity visualizations. Left heatmap: EMA factor $\eta$ vs control-plane interval $T_{cp}$ . Right heatmap: query feature dimension $m$ vs value dimension $d_{v}$ . The annotated operating point marks Chimera’s chosen configuration.

Figure 10: 24-hour deployment stability. Chimera with two-timescale adaptation maintains near-constant F1 across diurnal load; Fast-Only and Static-Map baselines exhibit drift or abrupt drops.

Configuration	F1	Bits/Flow	TCAM	Latency	Throughput
Attention Mechanism
Exact Softmax †	0.952	$>10^{4}$	0	2840 $\mu$ s	0.1Gbps
Linearized (Chimera)	0.950	30	256	0.9 $\mu$ s	100Gbps
Random Fourier Features	0.945	30	256	0.9 $\mu$ s	100Gbps
Key Selection Strategy
Local-Only ( $\mathcal{L}_{t}$ )	0.914	18	0	0.8 $\mu$ s	100Gbps

Table 3: Ablation of core architectural components on CICIOT. Configurations marked with † require control-plane offloading and violate line-rate constraints.

Query Features ( $m$ )	Value Dim ( $d_{v}$ )	Quantization	Aggregated State	Budget Ratio	CICIOT F1	PeerRush F1
64	32	16-bit	2KB	200%	0.9230	0.9450
64	64	16-bit	4KB	400%	0.9380	0.9720
128	32	16-bit	4KB	400%	0.9470	0.9840
128	64	16-bit	8KB	800%	0.9480	0.9840
128	32	8-bit	2KB	200%	0.9150	0.9380
128	64	8-bit	4KB	400%	0.9280	0.9560

Table 4: Hyperparameter sensitivity of feature dimensions and quantization on CICIOT. Configurations marked with † violate Eq. ( 11 ) per-flow SRAM budget (

<1

KB). Bold indicates Chimera’s operational setting.

EMA Factor ( $\eta$ )	Memory Depth	Update Interval ( $T_{cp}$ )	Budget Ratio	Table Churn	CICIOT F1	Stability
0.05	20 epochs	60s	0.08%	Negligible	0.9460	Slow response
0.10	10 epochs	60s	0.08%	Negligible	0.9500	Balanced
0.30	3 epochs	60s	0.08%	Negligible	0.9480	Noise sensitive
0.50	2 epochs	60s	0.08%	Low	0.9410	Oscillation risk
0.10	10 epochs	10s	0.45%	High	0.9480	Severe churn
0.10	10 epochs	300s	0.017%	Negligible	0.9490	Minor drift

Table 5: System stability across EMA factors and control-plane update intervals.

\eta

denotes EMA smoothing factor from Eq. ( 17 );

T_{cp}

denotes control-plane interval from Eq. ( 18 ). Budget ratio indicates

\Delta t_{\mathrm{install}}/T_{cp}

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Event-Driven Language Models with Sparse Neural Activity for Neuromorphic Hardware

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Department of Electrical and Computer Engineering, Aarhus University, Aarhus, Denmark · Department of Computer Science and Engineering, University of California, Santa Cruz, Santa Cruz, USA · School of Engineering and Applied Sciences, Harvard University, Cambridge, USA+1

Activation Sparsity LLM Inference Acceleration Neuromorphic Computing

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Inference with transformer-based large language models (LLMs) is often limited by the memory-bound KV cache and quadratic attention cost. State-space models (SSMs) mitigate this through linear attention and fixed-size recurrent states, but their large dense linear projections remain computationally expensive even after quantization. We introduce a method that induces sparse neural activity in heavily quantized linear-attention models with minimal performance loss. Activations below a per-projection trainable threshold (

\pm Δ

) are nullified while preserving crucial outliers, achieving comparable performance to dense models with up to 4

\times

fewer effective arithmetic operations. Targeting a multi-core, multi-chip neuromorphic platform, where event-driven execution converts unstructured sparsity into throughput at both the compute and communication levels, a capability GPU architectures fundamentally lack, we project up to 37

\times

higher throughput and 16

\times

lower power versus edge GPU inference of a comparable transformer-based model, and up to 5.4

\times

improvements over the non-sparsified baseline. These results position sparse, quantized linear-attention models as a natural fit for deploying LLMs on event-driven multi-core platforms.

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