Enabling Low-Latency Machine learning on Radiation-Hard FPGAs with hls4ml

Katya Govorkova; Julian Garcia Pardinas; Vladimir Loncar; Victoria Nguyen; Sebastian Schmitt; Marco Pizzichemi; Loris Martinazzoli; Eluned Anne Smith

hep-exFeb 17, 2026

Enabling Low-Latency Machine learning on Radiation-Hard FPGAs with hls4ml

Authors: Katya Govorkova, Julian Garcia Pardinas, Vladimir Loncar, Victoria Nguyen, Sebastian Schmitt, Marco Pizzichemi, Loris Martinazzoli, Eluned Anne Smith

Organizations: Massachusetts Institute of Technology (MIT), 77 Massachusetts Ave, Cambridge, MA 02139, USA · Department of Experimental Physics, European Organization for Nuclear Research (CERN), 1211 Geneva 23, Switzerland · University of Milano-Bicocca (Italy), and Department of Experimental Physics, European Organization for Nuclear Research (CERN), 1211 Geneva 23, Switzerland

Abstract

This paper presents an end-to-end demonstration of a viable, ultra-fast, radiation-hard machine learning (ML) application on FPGAs, which could be used in future high-energy physics experiments. We present a three-fold contribution, with the PicoCal calorimeter, planned for the LHCb Upgrade II experiment, used as a test case. First, we develop a lightweight autoencoder to compress a 32-sample timing readout, representative of that of the PicoCal, into a two-dimensional latent space. Second, we introduce a systematic, hardware-aware quantization strategy and show that the model can be reduced to 10-bit weights with minimal performance loss. Third, as a barrier to the adoption of on-detector ML is the lack of support for radiation-hard FPGAs in the High-Energy Physics community's standard ML synthesis tool, hls4ml, we develop a new backend for this library. This new back-end enables the automatic translation of ML models into High-Level Synthesis (HLS) projects for the Microchip PolarFire family of FPGAs, one of the few commercially available and radiation hard FPGAs. We present the synthesis of the autoencoder on a target PolarFire FPGA, which indicates that a latency of 25 ns can be achieved. We show that the resources utilized are low enough that the model can be placed within the inherently protected logic of the FPGA. Our extension to hls4ml is a significant contribution, paving the way for broader adoption of ML on FPGAs in high-radiation environments.

Figures & tables

Figure 1: Training and validation loss curves for the full-precision autoencoder (in green) and the quantized autoencoder (in pink), discussed fully in Sec. 4 . The y-axis uses a logarithmic scale to emphasize convergence behavior.

Figure 2: Examples of autoencoder reconstruction performance on calorimeter pulse shapes from the test set. Original waveforms (solid blue lines) are compared with their corresponding reconstructions (dashed/dotted lines). In green is the full precision model (AE), in pink is the quantized model that produced the latent space running on the actual hardware (FPGA). The orange line is also produced from a the latent space running on the actual hardware, but uses a more aggressively quantized model (nano-FPGA), discussed in Sec. 4 . Visual agreement is supported by low MSE values across diverse pulse amplitudes, highlighting the robustness of the reconstruction.

Figure 3: Correlation between latent space variables of the full-precision autoencoder and three pulse-level features on the test set: rise time (10%–90% interval), pulse true timestamp, and peak amplitude. Each row corresponds to one latent dimension ( $z[0],z[1]$ ), and each column to one feature. Scatter plots include Pearson’s $r$ and Spearman’s $\rho$ coefficients in the titles. The latent representation is strongly correlated with peak amplitude, while correlations with timing features (rise time and cell time) are weaker.

Panel of Figure 4 — Figure 4: Residual distributions between CFD-reconstructed timestamps and true simulation times for original and autoencoder-reconstructed pulses (left), and the ratio of their absolute values (right). Reconstruction systematically reduces the timing residual for approximately half of the events.

Figure 5: Histogram of the ratio of absolute differences in 10–90 % rise time: (reconstructed vs. 32-sample original) relative to (32-sample original vs. 1024-sample original).

Figure 6: Timestamp–residual distributions for the timestamps predicted using linear regression. The panel shows the histogram of $\Delta t=\hat{t}-t_{\mathrm{true}}$ ; the legend reports the mean $\mu$ and standard deviation $\sigma$ . All values are in units of samples.

Panel of Figure 7 — Figure 7: The impact of quantization on the autoencoder’s reconstruction performance (left). The average Mean Squared Error (MSE) is evaluated on the test dataset for different fixed-point bit widths. The green dashed line shows the MSE for non-quantized model. On the right is the distribution of the test MSE for the full precision model vs quantized to 10 bits.

FPGA setup		Value
FPGA setup		II	Latency	$f_{\rm max}$ [MHz]	LUTs	DFFs
MPF100T	FPGA	4	24	$180$	$7956$ ( $7.3\%$ )	$5893$ ( $5.4\%$ )
MPF100T	nFPGA	3	4	$280$	$3221$ ( $3.0\%$ )	$2059$ ( $1.9\%$ )
MPF300TS	FPGA	4	24	$212$	$7953$ ( $2.7\%$ )	$5825$ ( $1.9\%$ )
MPF300TS	nFPGA	3	4	$309$	$3211$ ( $1.1\%$ )	$1861$ ( $0.6\%$ )
Libero MPF300TS	FPGA	4	24	$212$	$5578$ ( $1.9\%$ )	$6383$ ( $2.1\%$ )

Table 1: Post-synthesis resource utilization per channel and performance for the autoencoder model on a Microchip PolarFire MPF100T-FCVG484I and MPF300TS-FCG1152I FPGA. The utilisation is quoted for the nano-FPGA and full FPGA model using the extrapolation from SmartHLS and the Libero Design suite, which is used to program the FPGA. The target clock frequency for every scenario is 160 MHz (6.25 ns period). The initiation interval (II) and latency are given in units of clock cycles. The Libero MPF300TS row indicates the performance numbers obtained by running the algorithm on the actual MPF300TS FPGA, as opposed to via co-simulation.

Figure 8: The floorplan of the nFPGA model. The core functionality includes the encoder, UART communication, and storage of weights and biases. For the encoder logic, separate markers are used to illustrate what operations are performed. N/A collects everything else from LED toggles to reset switches. The floorplan is zoomed in for visualization purposes.

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