Pareto Optimal Benchmarking of AI Models on ARM Cortex Processors for Sustainable Embedded Systems

Pranay Jain; Maximilian Kasper; Göran Köber; Oliver Amft; Axel Plinge; Dominik Seuß

cs.AIFeb 19, 2026

Pareto Optimal Benchmarking of AI Models on ARM Cortex Processors for Sustainable Embedded Systems

Authors: Pranay Jain, Maximilian Kasper, Göran Köber, Oliver Amft, Axel Plinge, Dominik Seuß

Organizations: Fraunhofer Institute for Integrated Circuits IIS, Germany · Intelligent Embedded Systems (IES) - Lab, University of Freiburg, Germany · Hahn-Schickard, Germany · Center for Artificial Intelligence and Robotics (CAIRO), Technische Hochschule Würzburg-Schweinfurt, Germany

Abstract

This work presents a practical benchmarking framework for optimizing artificial intelligence (AI) models on ARM Cortex processors (M0+, M4, M7), focusing on energy efficiency, accuracy, and resource utilization in embedded systems. Through the design of an automated test bench, we provide a systematic approach to evaluate across key performance indicators (KPIs) and identify optimal combinations of processor and AI model. The research highlights a nearlinear correlation between floating-point operations (FLOPs) and inference time, offering a reliable metric for estimating computational demands. Using Pareto analysis, we demonstrate how to balance trade-offs between energy consumption and model accuracy, ensuring that AI applications meet performance requirements without compromising sustainability. Key findings indicate that the M7 processor is ideal for short inference cycles, while the M4 processor offers better energy efficiency for longer inference tasks. The M0+ processor, while less efficient for complex AI models, remains suitable for simpler tasks. This work provides insights for developers, guiding them to design energy-efficient AI systems that deliver high performance in realworld applications.

Figures & tables

Platform	Freq.	Memory	Storage	Power	Price	CO2 Footprint
Cloud	GHz	$>10$ $\text{\,}\mathrm{GB}$	TBs-PBs	$\approx$ $1\text{\,}\mathrm{kW}$	$>1000$$	Hundreds of kgs
Mobile	GHz	Few GBs	GBs	$\approx$ $1\text{\,}\mathrm{W}$	$>100$$	Tens of kgs
Edge AI	MHz	KBs	Few MBs	$\approx$ $1\text{\,}\mathrm{mW}$	$>10$$	Single kgs

Table 1: Cloud vs. mobile vs. edge AIsystems across different parameters

Figure 1: Overview of the test bench architecture and workflow.

Use case	Model	#Params	Dataset	Quality Target
Image Classification	ResNet [ 5 , 9 ]	78k	CIFAR-10 [ 10 ]	$\geq$ 80\text{,}\mathrm{%}$$
Optical Digit Recognition	LeNet-5 [ 11 ]	140k	MNIST [ 11 ]	$\geq$ 95\text{,}\mathrm{%}$$
Anomaly Detection	Autoencoder [ 5 ]	269k	ToyADMOS [ 12 ]	AUC $\geq$ 85\text{,}\mathrm{%}$$
Visual Wake Words	MobileNetV1 [ 13 ]	3198k	MSCOCO14 [ 14 ]	$\geq$ 80\text{,}\mathrm{%}$$

Table 2: Overview of benchmark AIuse-cases

Figure 2: Experimental setup for test bench evaluation.

Figure 3: Benchmarking flow diagram (left) and exemplary current measurement (right).

Figure 4: Mean AImodel sizes per use-case.

Figure 5: Linear dependency between inference time and FLOPs.

Figure 6: Process flow for model selection and inference metrics prediction.

Figure 7: Inference cycle current and energy vs cycle time across processors for the smallest and largest models.

Figure 8: Energy vs. accuracy trade-offs for M4 and M7 across short, medium, and long inference cycles. Pareto fronts highlight optimal choices per workload.

Energy-Efficient ML

Energy-efficient machine learning reduces the energy and environmental costs of training and inference while preserving useful model performance.

See all 249 papers

Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review
Feb 18, 2026Luigi Capogrosso, Pietro Bonazzi, Michele MagnoIn-Sensor Computing Edge AI
Interdisciplinary Transformation University of Austria · ETH Zurich
WattLayer: Get Layers Right to Estimate Inference Energy of Neural Networks
Jun 26, 2026Adrien Sardi, Marie-Line Alberi Morel, Sara Alouf +2Energy-Efficient ML
Bell Labs, Nokia Networks France · Inria, Université Côte d’Azur, France · Université Côte d’Azur, CNRS, Inria, I3S, France
The Battery Price of edge AI: A study of the Environmental Impact of LLM Inference on Mobile Devices
Sep 14, 2026Édouard Guégain, Tristan CoignionOn-Device Language Model Inference Energy-Efficient ML
DRI, GREENSPECTOR · Univ. Bordeaux, CNRS, Bordeaux INP, LaBRI, UMR 5800, Talence, France

Feb 18, 2026J/K move · Enter open · S save

Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review

Luigi Capogrosso, Pietro Bonazzi, Michele Magno

Interdisciplinary Transformation University of Austria · ETH Zurich

In-Sensor Computing Edge AI Efficient Neural Network Inference Heterogeneous Computing

Open paper AskPDF arXiv

This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow and memory-centric designs. We categorize commercially available and research-grade platforms according to their compute paradigms, power envelopes, and memory hierarchies, and analyze their suitability for always-on and latency-critical Artificial Intelligence (AI) workloads. To complement the architectural overview with empirical evidence, we benchmark a 336 million Multiply-Accumulate (MAC) segmentation model (PicoSAM2) on three representative processors: GAP9, leveraging a multi-core RISC-V architecture augmented with hardware accelerators; the STM32N6, which pairs an advanced ARM Cortex-M55 core with a dedicated neural architecture accelerator; and the Sony IMX500, representing in-sensor stacked-Complementary Metal-Oxide-Semiconductor (CMOS) compute. Collectively, these platforms span MCU-class, embedded neural accelerator, and in-sensor paradigms. The evaluation reports latency, inference efficiency, energy efficiency, and energy-delay product. The results show a clear divergence in hardware behavior, with the IMX500 achieving the highest utilization (86.2 MAC/cycle) and the lowest energy-delay product, highlighting the growing significance and technological maturity of in-sensor processing. GAP9 offers the best energy efficiency within microcontroller-class power budgets, and the STM32N6 provides the lowest raw latency at a significantly higher energy cost. Together, the review and benchmarks provide a unified view of the current design directions and practical trade-offs that are shaping the next generation of ultra-low-power and in-sensor AI processors.

Abstract

Energy-Efficient ML

Explore similar work

Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review

WattLayer: Get Layers Right to Estimate Inference Energy of Neural Networks

The Battery Price of edge AI: A study of the Environmental Impact of LLM Inference on Mobile Devices