This brief presents a runtime-adaptive, performance-enhanced vector engine featuring a low-resource, iterative CORDIC-based MAC unit for edge AI acceleration. The proposed design enables dynamic reconfiguration between approximate and accurate modes, exploiting the latency-accuracy trade-off for a wide range of workloads. Its resource-efficient approach further enables up to 4x throughput improvement within the same hardware resources by leveraging vectorised, time-multiplexed execution and flexible precision scaling. With a time-multiplexed multi-AF block and a lightweight pooling and normalisation unit, the proposed vector engine supports flexible precision (4/8/16-bit) and high MAC density. The ASIC implementation results show that each MAC stage can save up to 33% of time and 21% of power, with a 256-PE configuration that achieves higher compute density (4.83 TOPS/mm2 ) and energy efficiency (11.67 TOPS/W) than previous state-of-the-art work. A detailed hardware-software co-design methodology for object detection and classification tasks on Pynq-Z2 is discussed to assess the proposed architecture, demonstrating a scalable, energy-efficient solution for edge AI applications.
Figures & tables
Design
Baseline
ICIIS’25 [ 11 ]
ICIIS’25 [ 11 ]
IEEE Access’24 [ 2 ]
TVLSI’25 [ 3 ]
ISCAS’25 [ 4 ]
ISVLSI’25 [ 5 ]
Proposed
Compute
Pipe-CORDIC
Pipe-CORDIC
PWL
Pipe-CORDIC
Pipe-CORDIC
Logarithmic Approx.
Iterative CORDIC
Iterative CORDIC
Arch. Type
Fully Parallel
Layer-Reused
NAF-Reused
NAF-Reused
Systolic Array
Time-multiplexed Reconfigurable Array
Layer-Reused
Vector Engine
Scalability
No
Yes
No
No
-
Yes
No
Yes
Precision
FxP-8
FxP-8
FxP-8
FxP-8
FxP-4/8/16/32
Posit-8/16/32
FxP-8
FxP-4/8/16
Accuracy loss
High
High
High
High
Medium
Low
Medium
Variable (Low)
Design Overhead
Area, St. Power
Area
Area, St. Power
Area, Power
Energy
Area, Complexity
Latency
Application-optimized High-Throughput
TABLE I: SoTA Design approaches and comparison of respective design features in AI workloads
Fig. 1: Block-level architecture of the proposed CORDIC-based vector engine integrated within a resource-efficient deep learning accelerator.
Fig. 2: Control Engine for efficient reuse of data and control signals in a layer-multiplexed for reusing the same DNN architecture.
Fig. 3: DNN accelerator data flow and order to initialise the loading data.
Fig. 4: Memory mapping scheme for address bits that requires addressing weights and bias for the individual neurons.
Fig. 5: Iterative low-latency CORDIC-based MAC architecture with runtime-configurable iteration depth.
Fig. 6: Hardware AAD module for two inputs.
Fig. 7: Hardware AAD module architecture based on sliding window
Fig. 8: Hardware AAD module architecture based on parallel computation.
Fig. 9: Multiple feature computations in parallel in hardware.
Fig. 10: Time-multiplexed Activation function with integrated data flow and control signals.
Design
TCAS-II’24 [ 29 ]
ISCAS’25 [ 4 ]
ICIIS’25 [ 11 ]
TVLSI’25 [ 30 ]
TCAD’22 [ 31 ]
TVLSI’25 [ 3 ]
Proposed
FPGA Utilization (VC707, 100 MHz)
Parameter
FP32
FP32
BF16
Posit-8
Vedic
Wallace
Booth
Quant-MAC
CORDIC
MSDF-MAC
Acc-App-MAC
CORDIC
Iter-MAC
LUTs
8065
8054
3670
467
160
106
84
72
56
62
57
45
24
FFs
1072
1718
324
175
241
113
59
56
72
45
NR
37
22
Delay (ns)
5.56
4.6
0.512
2.68
4.5
2.6
3.1
5.4
1.52
3.2
3.51
4.5
9.1
Power (mW)
378
296
136
68
6.1
3.3
3.1
4.2
8.3
5.8
6.9
2
1.9
TABLE II: Comparative Performance Metrics for CORDIC-based different SoTA MAC units
Design
ISQED’24 [ 32 ]
TCAS-II’20 [ 33 ]
TVLSI’23 [ 34 ]
ISQED’24 [ 32 ]
TC’23 [ 35 ]
ISQED’24 [ 32 ]
TVLSI’25 [ 3 ]
Proposed
FPGA Utilization (VC707, 100 MHz)
Parameter
Softmax-FP32
Softmax-FP16
Softmax-BF16
Softmax- FxP8/16
Softmax-16b
Tanh-FP32
Tanh-FP16
Tanh-BF16
Tanh/Sigmoid-16b
Sigmoid-FP32
Sigmoid-FP16
Sigmoid-BF16
SSTp
FxP-4/8/16
LUTs
3217
1137
1263
2564
1215
4298
1530
1513
2395
5101
1853
1856
897
537
FFs
NR
NR
NR
2794
1012
NR
NR
NR
1503
NR
NR
NR
1231
468
Delay (ns)
92
43
45
2.3
3.32
56
34
38
0.18
109
60
45
11.8
2.6
Power (mW)
115
115
77
NR
165
130
124
82
681
121
118
83
59
30
TABLE III: Comparative Performance Metrics for CORDIC-based different SoTA AF units
Fig. 11: Evaluation of DNN accuracy for different DNN models with CORDIC methodology.
Design
Platform
Precision
k-LUTs
k-Regs/FFs
DSPs
Op. Freq (MHz)
Energy efficiency (GOPS/W)
Power(W)
Proposed
VC707
4/8/16
26.7
15.9
-
85.4
6.43
0.53
TVLSI’25 [ 3 ]
VC707
4/8/16/32
38.7
17.4
73
466
8.42
2.24
TCAS-I’24 [ 37 ]
ZU3EG
8
40.8
45.5
258
100
0.39
2.2
TCAS-II’23 [ 38 ]
XCVU9P
8
132
39.5
96
150
6.36
5.52
TVLSI’23 [ 39 ]
ZCU102
8
117
74
132
300
4.2
6.58
Access’24 [ 2 ]
VC707
4/8
19.8
12.1
39
136
0.68
1.81
TABLE IV: Analysis of FPGA Hardware Implementation for object detection (TinyYolo-v3) with SoTA AI accelerator designs
Fig. 12: Prototype visualisation, showing Pynq-z2 for edge AI inference on Unmanned Aerial Vehicles (UAV).
Design
Network/Arch
Datatype
Freq. (GHz)
Area (mm 2 )
Power (mW)
Energy Efficiency TOPS/W
Compute Density TOPS/mm 2
TCAS-II’24 [ 29 ]
Vector Engine (64 × MACs)
FP8
1.47
0.896
1622
7.24
2.39
1.29
1.18
1375
3.57
1.21
TCAS-I’22 [ 1 ]
Vector Engine (64 × MACs) 196-64-32-32-10
INT-8
0.4
2.43
224.6
7.75
1.67
ISCAS’25 [ 4 ]
TREA (64 × MACs) 196-64-32-32-10
Posit-8
1.25
6.73
230.4
7.55
0.16
TVLSI’25 [ 3 ]
Systolic Array (8x8)
FxP8
0.44
1.85
523
4.3
2.76
ICIIS’25 [ 11 ]
Layer-Reused (64 × MACs) 196-64-32-32-10
FxP8
0.25
3.78
1540
4.28
2.07
TABLE V: ASIC performance comparison with SoTA 8-bit accelerator designs, with CMOS 28nm, 0.9V, SF technology.
Fig. 13: VGG-16 layer-wise execution time and power consumption.
AI accelerator inference studies hardware and software for running neural networks faster and more efficiently across data-center, edge, and mobile devices.