GPU architectural simulation is orders of magnitude slower than native execution, necessitating workload sampling for practical speedups. Existing methods rely on hand-crafted features with limited expressiveness, yielding either aggressive sampling with high errors or conservative sampling with constrained speedups. To address these issues, we propose GCL-Sampler, a sampling framework that leverages Relational Graph Convolutional Networks with contrastive learning to automatically discover high-dimensional kernel similarities from trace graphs. By encoding instruction sequences and data dependencies into graph embeddings, GCL-Sampler captures rich structural and semantic properties of program execution, enabling both high fidelity and substantial speedup. Evaluations on extensive benchmarks show that GCL-Sampler achieves 258.94x average speedup against full workload with 0.37% error, outperforming state-of-the-art methods, PKA (129.23x, 20.90%), Sieve (94.90x, 4.10%) and STEM+ROOT (56.57x, 0.38%).
Figures & tables
Figure 1. GCL-Sampler achieves near-ideal performance (red star) with minimal error and maximum speedup compared to existing methods.
Figure 2. Overview of GCL-Sampler. GCL-Sampler transforms program traces into HRGs and leverages RGCN-based contrastive learning to generate kernel embeddings, followed by K-Means clustering.
Component
Description
tbx , tby , tbz
CTA coordinates in the grid
warp_id
Warp identifier within the CTA
PC
Program counter
mask
32-bit active lane mask
#dests
Number of destination registers
[dest_regs]
Destination register identifiers
Table 1. Trace components for each instruction.
Figure 3. An example of graph construction from traces.
CPU (Intel)
GPU
Architecture
P1
E5-2680 v4
RTX 2080Ti
Turing
P2
i9-12900KF
RTX 3080Ti
Ampere
P3
W5-3435X
RTX 4090
Ada Lovelace
Table 2. Hardware configurations for experiments.
Figure 4. Sampling error of GCL-Sampler, PKA, Sieve and STEM+ROOT. A woman and a girl in white dresses sit in an open car.
Figure 5. Speedup of GCL-Sampler, PKA, Sieve and STEM+ROOT. A woman and a girl in white dresses sit in an open car.
Program
P1
P2
P3
E (%)
SU
E (%)
SU
E (%)
SU
bfs
1.07
3.04 ×
<0.01
3.17 ×
0.05
3.51 ×
lu
0.92
2224.67 ×
0.11
1644.30 ×
<0.01
1658.56 ×
phi-2
0.63
18.41 ×
10.44
13.42 ×
9.74
14.01 ×
qwen1.5
0.38
5.19 ×
2.20
3.76 ×
1.93
3.81 ×
3mm
0.71
3.05 ×
1.61
3.00 ×
0.67
3.03 ×
Table 3. Sampling error and speedup across GPU microarchitecture. P1 denotes Turing, P2 denotes Ampere, and P3 denotes Ada Lovelace. E(%)=Error(in %), SU=Speedup.
Figure 6. Microarchitectural metrics comparison between sampled and full simulation for cfd and pythia workloads.