Saarthi is an agentic AI framework that uses multi-agent collaboration to perform end-to-end formal verification. Even though the framework provides a complete flow from specification to coverage closure, with around 40% efficacy, there are several challenges that need to be addressed to make it more robust and reliable. Artificial General Intelligence (AGI) is still a distant goal, and current Large Language Model (LLM)-based agents are prone to hallucinations and making mistakes, especially when dealing with complex tasks such as formal verification. However, with the right enhancements and improvements, we believe that Saarthi can be a significant step towards achieving domain-specific general intelligence for formal verification. Especially for problems that require Short Term, Short Context (STSC) capabilities, such as formal verification, Saarthi can be a powerful tool to assist verification engineers in their work. In this paper, we present two key enhancements to the Saarthi framework: (1) a structured rulebook and specification grammar to improve the accuracy and controllability of SystemVerilog Assertion (SVA) generation, and (2) integration of advanced Retrieval Augmented Generation (RAG) techniques, such as GraphRAG, to provide agents with access to technical knowledge and best practices for iterative refinement and improvement of outputs. We also benchmark these enhancements for the overall Saarthi framework using challenging test cases from NVIDIA's CVDP benchmark targeting formal verification. Our benchmark results stand out with a 70% improvement in the accuracy of generated assertions, and a 50% reduction in the number of iterations required to achieve coverage closure.
Figures & tables
Fig. 1 : Overview of the basic RAG pipeline [ 27 ]
Fig. 2 : Knowledge graph construction and retrieval in GraphRAG pipeline [ 13 ]
Fig. 3 : Saarthi: Agentic AI based formal verification using multi-agent collaboration
Fig. 4 : Data Collection Flow during HIL
Fig. 5 : A snippet of the cached mistakes that all agents can learn from for future iterations
Fig. 6 : A comparison of the iterative SVA generation process before and after adding the rulebook
Fig. 7 : Overview of the comprehensive multi-agent RCA setup
Design
Metric
Pass@1
Pass@2
Pass@3
GPT-4.1
GPT-5
Llama3.3
GPT-4.1
GPT-5
Llama3.3
GPT-4.1
GPT-5
Llama3.3
ECC
# Assertions
19
28
14
25
32
6
25
48
12
1st generation
No
Yes
No
Yes
Yes
Yes
No
Yes
Yes
# attempts to fix
1
0
2
0
0
0
2
0
0
% Proven
71.86%
89.28%
57.14%
64.00%
75.00%
33.33%
64.00%
81.25%
50.00%
% Coverage
62.67%
58.57%
68.01%
60.21%
61.86%
2.18%
58.15%
93.74%
43.90%
TABLE I : Key Performance Indicators of Saarthi on designs of various complexity
Fig. 8 : Radar chart for Pass@1 for different designs
Fig. 9 : Radar chart for Pass@2 for different designs
Fig. 10 : Radar chart for Pass@3 for different designs
Design
Metric
Without HIL
With HIL
GPT-4.1
GPT-5
Llama3.3
GPT-4.1
GPT-5
Llama3.3
ECC
# Assertions
53
66
19
53
60
19
% Proven
84.90%
78.80%
68.42%
96.06%
80.00%
84.21%
% Coverage
89.31%
92.83%
90.63%
98.05%
95.22%
92.53%
Automotive IP
# Assertions
36
58
19
36
58
19
% Proven
50%
84.48%
26.31%
72.22%
93.10%
63.15%
TABLE II : Coverage improvement with and without HIL at Pass@1
Design
Metric
Coverage improvement without HIL
1 st Iter
2 nd Iter
3 rd Iter
4 th Iter
5 th Iter
ECC
# Assertions
312
318
1258
N/A
N/A
% Proven
91.67%
92.12%
97.93%
N/A
N/A
% Coverage
88.89%
86.86%
87.87%
N/A
N/A
Automotive IP
# Assertions
59
71
134
185
233
% Proven
81.35%
77.46%
85.82%
87.75%
89.69%
TABLE III : Coverage improvement without HIL across iterations (GPT-5)
Fig. 11 : % Proven comparison with and without HIL at Pass@1
Fig. 12 : Coverage comparison with and without HIL at Pass@1
Coverage closure is a critical requirement in Integrated Chip (IC) development process and key metric for verification sign-off. However, traditional exhaustive approaches often fail to achieve full coverage within project timelines. This study presents an agentic AI-driven workflow that utilizes Large Language Model (LLM)-enabled Generative AI (GenAI) to automate coverage analysis for formal verification, identify coverage gaps, and generate the required formal properties. The framework accelerates verification efficiency by systematically addressing coverage holes. Benchmarking open-source and internal designs reveals a measurable increase in coverage metrics, with improvements correlated to the complexity of the design. Comparative analysis validates the effectiveness of this approach. These results highlight the potential of agentic AI-based techniques to improve formal verification productivity and support comprehensive coverage closure.
Infineon Technologies India Private Limited, India · Dr. B R Ambedkar National Institute of Technology Jalandhar, India · Infineon Technologies Dresden AG & Co. KG, Germany
Recent advances in Large Language Models (LLMs) have enabled workflows that generate SystemVerilog Assertions (SVAs) from natural-language specifications, with the potential to accelerate Formal Verification (FV). However, high-quality assertion synthesis remains challenging because specifications are often ambiguous or incomplete and critical micro-architectural details reside in the Register Transfer Level (RTL). Many existing approaches treat the specification and RTL as loosely structured text, which weakens specification-to-RTL grounding and leads to semantic mismatches and frequent syntax failures during formal parsing and elaboration. This work addresses these limitations with a verification-centric Knowledge Graph (KG) constructed from structured Intermediate Representations (IRs) extracted from the specification, RTL, and formal-tool feedback, including syntax diagnostics, Counterexamples (CEXs), and coverage reports. The KG links requirements, design hierarchy, signals, assumptions, and properties to provide traceable, design-grounded context for generation. A multi-agent workflow queries and updates this KG to generate SVAs and to drive three refinement loops: syntax repair guided by tool diagnostics, CEX-guided correction using trace links, and coverage-directed property augmentation. Evaluation across seven benchmark designs indicates that KG-based context retrieval improves specification-to-RTL grounding and consistently produces compilable SVAs with low syntax-repair overhead. The approach achieves formal coverage ranging from 78.5% to 99.4%, though convergence exhibits design dependence with complex temporal and arithmetic reasoning remaining challenging for current LLM capabilities.
Functional verification consumes over 50% of the IC development lifecycle, where SystemVerilog Assertions (SVAs) are indispensable for formal property verification and enhanced simulation-based debugging. However, manual SVA authoring is labor-intensive and error-prone. While Large Language Models (LLMs) show promise, their direct deployment is hindered by low functional accuracy and a severe scarcity of domain-specific data. To address these challenges, we introduce ChatSVA, an end-to-end SVA generation system built upon a multi-agent framework. At its core, the AgentBridge platform enables this multi-agent approach by systematically generating high-purity datasets, overcoming the data scarcity inherent to few-shot scenarios. Evaluated on 24 RTL designs, ChatSVA achieves 98.66% syntax and 96.12% functional pass rates, generating 139.5 SVAs per design with 82.50% function coverage. This represents a 33.3 percentage point improvement in functional correctness and an over 11x enhancement in function coverage compared to the previous state-of-the-art (SOTA). ChatSVA not only sets a new SOTA in automated SVA generation but also establishes a robust framework for solving long-chain reasoning problems in few-shot, domain-specific scenarios. An online service has been publicly released at https://www.nctieda.com/CHATDV.html.
Lik Tung Fu, Jie Zhou, Shaokai Ren +6
National ASIC Center, School of Integrated Circuits, Southeast University, China · National Center of Technology Innovation for Electronic Design Automation, China · Department of Computer Science, City University of Hong Kong, Hong Kong, China