mlx-snn: Spiking Neural Networks on Apple Silicon via MLX

Jiahao Qin

cs.LGMar 3, 2026

mlx-snn: Spiking Neural Networks on Apple Silicon via MLX

Authors: Jiahao Qin

Abstract

We introduce mlx-snn, the first spiking neural network (SNN) library built natively on Apple's MLX framework. As SNN research grows rapidly, all major libraries -- snnTorch, Norse, SpikingJelly, Lava -- target PyTorch or custom backends, leaving Apple Silicon users without a native option. mlx-snn provides six neuron models (LIF, IF, Izhikevich, Adaptive LIF, Synaptic, Alpha), four surrogate gradient functions, four spike encoding methods (including an EEG-specific encoder), and a complete backpropagation-through-time training pipeline. The library leverages MLX's unified memory architecture, lazy evaluation, and composable function transforms (mx.grad, mx.compile) to enable efficient SNN research on Apple Silicon hardware. We validate mlx-snn on MNIST digit classification across five hyperparameter configurations and three backends, achieving up to 97.28% accuracy with 2.0--2.5 times faster training and 3--10 times lower GPU memory than snnTorch on the same M3 Max hardware. mlx-snn is open-source under the MIT license and available on PyPI. https://github.com/D-ST-Sword/mlx-snn

Figures & tables

Feature	mlx-snn	snnTorch	Norse	SpikingJelly	Lava
Backend	MLX	PyTorch	PyTorch	PyTorch	Custom
Neuron models	6	6	8	10+	4
Surrogate gradients	4	5	3	4	—
Spike encoding	4	4	2	3	—
Apple Silicon native	$\checkmark$	—	—	—	—
CUDA acceleration	—	$\checkmark$	$\checkmark$	$\checkmark$	—

Table 1: Feature comparison of SNN software libraries.

\checkmark

= supported,

\circ

= partial, — = not supported.

		mlx-snn (MLX)		snnTorch (MPS)		snnTorch (CPU)
	Hyperparameters	Acc. (%)	Time (s)	Acc. (%)	Time (s)	Acc. (%)	Time (s)
C1	$\beta{=}0.85,\;h{=}256,\;\text{lr}{=}10^{-3}$	97.28	4.0	98.00	8.8	98.01	12.8
C2	$\beta{=}0.9,\;h{=}256,\;\text{lr}{=}10^{-3}$	97.02	4.3	98.03	8.9	97.97	13.5
C3	$\beta{=}0.9,\;h{=}256,\;\text{lr}{=}10^{-3},\;B{=}256$	96.91	2.4	98.03	4.8	98.17	16.7
C4	$\beta{=}0.9,\;h{=}128,\;\text{lr}{=}10^{-3}$	96.90	4.3	97.84	9.0	97.74	10.9
C5	$\beta{=}0.95,\;h{=}128,\;\text{lr}{=}2{\times}10^{-3},\;15\text{ep}$	94.98	4.4	97.09	9.0	97.00	11.1

Table 2: MNIST classification: 5 hyperparameter configurations

\times

3 backends. All use the same

784

–

h

–

10

feedforward SNN with

T{=}25

timesteps, fast sigmoid surrogate, and batch size 128 unless noted. C1–C4 train for 25 epochs; C5 trains for 15 epochs. Acc. = best test accuracy over all epochs; Time = average seconds per epoch; Mem. = peak GPU allocator memory (Metal for mlx-snn, MPS for snnTorch).

Figure 1: MNIST training curves for configuration C5 (

\beta{=}0.95

h{=}128

). Left: test accuracy vs. epoch. Right: training time per epoch.

Figure 2: Membrane potential traces for all six neuron models with constant input current over 200 timesteps. Red vertical lines indicate spike events.

Surrogate Function	Test Accuracy (%)	Training Time (s)
Fast Sigmoid ( $k=25$ )	93.65	44.7
Arctan ( $\alpha=2$ )	92.44	43.8
Straight-Through ( $s=1$ )	46.28	46.3

Table 3: Surrogate gradient comparison on MNIST using baseline configuration (

\beta{=}0.95

h{=}128

, lr

=2{\times}10^{-3}

, 10 epochs). Note: this matches C5 in Table 2 , not the best configuration C1.

Figure 3: Surrogate gradient functions. Blue: forward pass (Heaviside step function). Red dashed: backward pass (smooth gradient used for BPTT).

Spiking Neural Networks

Spiking neural networks process information through discrete, time-dependent neural events, aiming for efficient computation and biologically inspired learning.

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Spiking Neural Network inference on FPGAs with hls4ml

Barry M. Dillon

ISRC, Ulster University, Derry, BT48 7JL, Northern Ireland

Efficient Neural Network Inference Spiking Neural Networks FPGA-Based Neural Network Acceleration

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Spiking Neural Networks (SNNs) provide a naturally temporal machine-learning framework. Their neurons maintain an internal state and propagate information through discrete spikes, enabling low-latency temporal inference. Although SNNs are often associated with asynchronous neuromorphic processors, many scientific real-time inference systems rely on conventional synchronous field-programmable gate arrays (FPGAs) and high-level synthesis (HLS) workflows. In this paper we present an extension of hls4ml that enables clock-driven deployment of SNNs trained in pytorch onto FPGA firmware. We demonstrate the workflow using a dense quantised SNN trained on the Heidelberg Spiking Digits dataset where it achieves inference latencies of approximately

34μ

s. We validate the generated design through software reference comparisons, HLS C simulation, HLS synthesis, export, and Vivado synthesis reports. This work opens up the hls4ml toolkit to neuromorphic computing, allowing streamlined optimisation, synthesis, and deployment of SNN models for real-time inference.

Abstract

Spiking Neural Networks

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