cs.ARFeb 18, 2026

Performance Analysis of Edge and In-Sensor AI Processors: A Comparative Review

Authors: Luigi Capogrosso, Pietro Bonazzi, Michele Magno

Organizations: Interdisciplinary Transformation University of Austria · ETH Zurich

Read PDF
Ask AI
Cite

Copy citation

DOINot available for this paper

Abstract

This review examines the rapidly evolving landscape of ultra-low-power edge processors, covering heterogeneous Systems-on-Chips (SoCs), neural accelerators, near-sensor and in-sensor architectures, and emerging dataflow and memory-centric designs. We categorize commercially available and research-grade platforms according to their compute paradigms, power envelopes, and memory hierarchies, and analyze their suitability for always-on and latency-critical Artificial Intelligence (AI) workloads. To complement the architectural overview with empirical evidence, we benchmark a 336 million Multiply-Accumulate (MAC) segmentation model (PicoSAM2) on three representative processors: GAP9, leveraging a multi-core RISC-V architecture augmented with hardware accelerators; the STM32N6, which pairs an advanced ARM Cortex-M55 core with a dedicated neural architecture accelerator; and the Sony IMX500, representing in-sensor stacked-Complementary Metal-Oxide-Semiconductor (CMOS) compute. Collectively, these platforms span MCU-class, embedded neural accelerator, and in-sensor paradigms. The evaluation reports latency, inference efficiency, energy efficiency, and energy-delay product. The results show a clear divergence in hardware behavior, with the IMX500 achieving the highest utilization (86.2 MAC/cycle) and the lowest energy-delay product, highlighting the growing significance and technological maturity of in-sensor processing. GAP9 offers the best energy efficiency within microcontroller-class power budgets, and the STM32N6 provides the lowest raw latency at a significantly higher energy cost. Together, the review and benchmarks provide a unified view of the current design directions and practical trade-offs that are shaping the next generation of ultra-low-power and in-sensor AI processors.

Figures & tables

Figure 1: Peak performance in TOPS vs. power consumption of publicly announced AI accelerators and processors. Data are from [ 10 , 11 , 12 , 13 ] .
HW Platform & Peak Perf. (TOPS) & Power (W) & Precision & HW Architecture & Efficiency (TOPS/W)
Netcast & 1.00E+01 & 0.001 & int8 & Dataflow ASIC & 1.00E+04
Ergo & 4.00E+00 & 0.073 & int8 & Tensor ASIC & 5.48E+01
Ethos N77 & 4.10E+00 & 0.800 & int8 & Tensor ASIC & 5.13E+00
MX3 & 5.00E+00 & 1.000 & fp16 & Manycore ASIC & 5.00E+00
Tianjic & 1.21E+00 & 0.950 & int8 & Neuromorphic & 1.27E+00
AML200 & 2.00E+00 & 0.100 & int8 & Analog In-Memory & 2.00E+01
Table I: Hardware performance comparison for devices under 2 W (sorted by Efficiency: TOPS/W). Data from [ 10 , 11 , 12 , 13 ] .
Figure 2: Benchmarking results of PicoSAM2 [ 25 ] , comparing its energy efficiency, latency, inference efficiency, and energy–delay product (EDP) on GAP9, STM32N6, and IMX500. The results highlight the advantages of in-sensor compute for improved energy efficiency and latency.
More in this topic

In-Sensor Computing

See all 10 papers

Explore similar work

CardsList
Feb 19, 2026

Pareto Optimal Benchmarking of AI Models on ARM Cortex Processors for Sustainable Embedded Systems

This work presents a practical benchmarking framework for optimizing artificial intelligence (AI) models on ARM Cortex processors (M0+, M4, M7), focusing on energy efficiency, accuracy, and resource utilization in embedded systems. Through the design of an automated test bench, we provide a systematic approach to evaluate across key performance indicators (KPIs) and identify optimal combinations of processor and AI model. The research highlights a nearlinear correlation between floating-point operations (FLOPs) and inference time, offering a reliable metric for estimating computational demands. Using Pareto analysis, we demonstrate how to balance trade-offs between energy consumption and model accuracy, ensuring that AI applications meet performance requirements without compromising sustainability. Key findings indicate that the M7 processor is ideal for short inference cycles, while the M4 processor offers better energy efficiency for longer inference tasks. The M0+ processor, while less efficient for complex AI models, remains suitable for simpler tasks. This work provides insights for developers, guiding them to design energy-efficient AI systems that deliver high performance in realworld applications.

Pranay Jain, Maximilian Kasper, Göran Köber +3

Fraunhofer Institute for Integrated Circuits IIS, Germany · Intelligent Embedded Systems (IES) - Lab, University of Freiburg, Germany · Hahn-Schickard, Germany +1

Energy-Efficient MLTiny ML
AskPDF
Apr 6, 2026

DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision floating-point MAC processing element supporting FP8 (E4M3, E5M2) and FP4 (2 x E2M1, 2 x E1M2) formats, specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4 x 4 multiplier for FP8 or as two parallel 2 x 2 multipliers for 2-bit operands, achieving maximum hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed PE achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4% area reduction and 86.6% power savings compared to state-of-the-art designs, making it well suited for energy-constrained AI inference and mixed-precision computing applications when deployed within larger accelerator architectures.

Shubham Kumar, Vijay Pratap Sharma, Vaibhav Neema +1

Institute of Engineering and Technology, Devi Ahilya University, Indore, India · NSDCS Research Group, Indian Institute of Technology Indore, India

AI Accelerator InferenceEnergy-Efficient ML
AskPDF
Apr 4, 2026

L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.

Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma

Centre for Advanced Electronics, Indian Institute of Technology Indore, Simrol 453552, Indore, India · Dept. of Electrical Engineering, Indian Institute of Technology Indore, Simrol 453552, Indore, India

Efficient Neural Network InferenceSpiking Neural NetworksFPGA-Based Neural Network AccelerationEdge Inference
AskPDF