DendroNN: Dendrocentric Neural Networks for Energy-Efficient Classification of Event-Based Data
Authors: Jann Krausse, Zhe Su, Kyrus Mama, Maryada, Klaus Knobloch, Giacomo Indiveri, Jürgen Becker
Organizations: Infineon Technologies, Dresden, Germany · Karlsruhe Institute of Technology, Karlsruhe, Germany · Institute of Neuroinformatics, University of Zurich and ETH Zurich, Zurich, Switzerland · Stanford University, Stanford, CA, USA · Retired, formerly Infineon Technologies, Dresden, Germany
Spatiotemporal information is at the core of diverse sensory processing and computational tasks. Feed-forward spiking neural networks can be used to solve these tasks while offering potential benefits in terms of energy efficiency by computing event-based. However, they have trouble decoding temporal information with high accuracy. Thus, they commonly resort to recurrence or delays to enhance their temporal computing ability which, however, bring downsides in terms of hardware-efficiency. In the brain, dendrites are computational powerhouses that just recently started to be acknowledged in such machine learning systems. In this work, we focus on a sequence detection mechanism present in branches of dendrites and translate it into a novel type of neural network by introducing a dendrocentric neural network, DendroNN. DendroNNs identify unique incoming spike sequences as spatiotemporal features. This work further introduces a rewiring phase to train the non-differentiable spike sequences without the use of gradients. During the rewiring, the network memorizes frequently occurring sequences and additionally discards those that do not contribute any discriminative information. The networks display competitive accuracies across various event-based time series datasets. We also propose an asynchronous digital hardware architecture using a time-wheel mechanism that builds on the event-driven design of DendroNNs, eliminating per-step global updates typical of delay- or recurrence-based models. By leveraging a DendroNN's dynamic and static sparsity along with intrinsic quantization, it achieves up to 4x higher efficiency than state-of-the-art neuromorphic hardware at comparable accuracy on the same audio classification task, demonstrating its suitability for spatiotemporal event-based computing. This work offers a novel approach to low-power spatiotemporal processing on event-driven hardware.
Figures & tables
Figure 1: (a) Schematic of the network architecture. Sparse, binary connections route input spikes x to a set of hidden units, each tuned to a specific spatiotemporal pattern. (b) Example of sequence detection for Ns=3 . A hidden unit responds only when spikes arrive from the correct spatial origins x0~,x1~,x2~ in the prescribed temporal order, with inter-spike intervals Δt1 and Δt2 . Inputs that are out of order or mistimed are suppressed. When the full target sequence is observed, the unit emits a single output spike.
Figure 2: Exemplary input spike patterns and model responses. (a) All input spikes arrive from the correct spatial channels and in the prescribed temporal order, with the required inter-spike intervals Δt1 and Δt2 , resulting in the emission of an output spike. (b) Although the spike order is preserved, deviations in the inter-spike intervals (early or late arrivals) violate the temporal constraints and suppress the output response. (c) Only the spikes belonging to the correctly ordered sequence (red) satisfy the spatiotemporal constraints; spikes from incorrectly ordered sequences do not elicit an output. (d) Multiple sequences can be processed in parallel: irrelevant spikes are inhibited, while all valid target sequences are reliably detected and trigger output events.
Figure 4: Visualization of the rewiring phase using the NeuroMorse train set sample "which" as an example. Throughout multiple epochs, initially randomly arranged sequences are rewired and frozen to match existing spatiotemporal patterns in the sample.
Figure 5: Impact of applying the rewiring phase regarding the model’s footprint. In the case of the NeuroMorse dataset, network size can be reduced by 10-100x without suffering accuracy loss. This effect is drastically amplified for datasets of higher spatial and temporal complexity.
Poissonian
Jitter
None
Low
High
Dropout
None
Low
High
None
Low
High
None
Low
High
Model
None
SNN [ 32 ]
12.27%
4.37%
2.48%
6.22%
2.49%
1.69%
5.70%
2.07%
1.66%
DendroNN*
90.22%
81.53%
75.18%
51.63%
51.55%
51.82%
52.29%
50.24%
51.94%
Low
SNN [ 32 ]
11.81%
4.30%
2.40%
6.26%
2.42%
1.65%
5.76%
2.00%
1.60%
DendroNN*
73.24%
68.79%
66.24%
51.79%
52.34%
50.55%
49.58%
50.85%
49.56%
Table 1: Benchmarking of DendroNN and SNN on the NeuroMorse dataset for classification of spike sequences.
Dataset
Model
Accuracy
Memory Footprint / MBit
sMNIST
SRNN [ 33 ]
10.00% +
1.42
Adaptive SRNN [ 33 ]
97.82%
1.42
LSNN (L2L+DeepR) [ 3 ]
96.40%
0.72
DendroNN*
97.50±0.11 %
1.71
DendroNN* (compressed)
96.23±0.15 %
1.27
p-sMNIST
SRNN [ 33 ]
10.00% +
2.15
Table 2: Benchmarking of DendroNN and other spiking models on smnist and psmnist for classification of time sequences. DendroNN results are averaged over 5 runs. Memory footprints are calculated using Equation ( 9 ). Memory sizes of references assume 32 bit parameters and do not include contribution of hidden and output unit states as well as delay buffers to the total memory footprint, the latter of which is expected to contribute significantly.
Model
Accuracy
\makecell Memory
Footprint / MBit
RSNN [ 20 ]
85.60%
8.00
SNN w/ random dend. delays [ 11 ]
90.1%
7.17 †
RSNN w/ learnable syn. delays [ 20 ]
93.2%
40.04 †
adLIF [ 2 ]
93.79%
14.40
DendroNN*
89.24±0.31 %
0.60
Table 3: Benchmarking of DendroNN other spiking models on the SHD dataset for classification of event-based data. DendroNN results are averaged over 5 runs. Memory footprints are calculated using Equation ( 9 ). Memory sizes of references assume 32 bit parameters and do not include contribution of hidden and output unit states as well as delay buffers to the total memory footprint, the latter of which is expected to contribute significantly.
Figure 6: A near-memory asynchronous digital computing architecture for DendroNN, along with a comparison of hardware metrics against other aggressively optimized platforms achieving comparable accuracy on the same task. (a) Hardware microarchitecture. Event data from the sensor are decoded into channel addresses using Address Event Representation (AER). Each entry in the connectivity router (CR) memory stores four sparse orthogonal indices corresponding to the postsynaptic unit and spine. Four parallel unit update engines (UEs) handle due-condition detection, new spike scheduling, and weight update operations. Spikes generated by the hidden units are propagated to the output classifier layer, which supports both spike-count–based decisions and neuron membrane potential–based decision making. (b) The Mousetrap asynchronous pipeline [ 29 ] is employed throughout the AER, UE, and output neuron logic. This pipeline offers minimal hardware cost and high operating speed. By eliminating the need for a global clock, it naturally aligns with the event-driven characteristics of DendroNN. (c) DendroNN (3) achieves up to 1.9× higher throughput than delay-based hardware, while providing comparable throughput to feedforward networks with significantly higher accuracy. (d) DendroNN (3) delivers up to 4.1× higher energy efficiency than delay-based hardware and 2.8× higher energy efficiency than recurrence-based hardware, primarily due to its fully event-driven architecture. (e) DendroNN achieves 2× higher area efficiency than recurrence-based hardware, mainly due to its binary weights and efficient spike-activity storage.
Hyperparameter
NeuroMorse
sMNIST & p-sMINST
SHD
#Units
200
1500
3000
max. #Spines
5
5
2
min. #Spines
2
5
3
ΔT
2
0
0
rpr
0.1
0.1
0.1
criterion
( 14 )
( 14 )
( 14 )
Table 4: Overview of the model hyperparameters chosen for the results of experiments presented in this work.
Research Center for Mathematical Engineering, Chiba Institute of Technology, Narashino, Japan · International Research Center for Neurointelligence (WPI-IRCN), The University of Tokyo, Tokyo, Japan · NEC Corporation, Kawasaki, Japan
Department of Computer Science, Columbia University, New York, NY, USA · Department of Neuroscience, Cold Spring Harbor Laboratory, Cold Spring Harbor, NY, USA