VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

Runbang Hu; Bo Fang; Bingzhe Li; Yuede Ji

cs.ARMar 10, 2026

VeriHGN: Heterogeneous Graph-Based Congestion Prediction for Chip Layout Verification

Authors: Runbang Hu, Bo Fang, Bingzhe Li, Yuede Ji

Organizations: The University of Texas at Arlington, Arlington, Texas, USA · The University of Texas at Dallas, Dallas, Texas, USA

Abstract

As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate that VeriHGN achieves the best or near-best performance over state-of-the-art methods in prediction accuracy and correlation metrics.

Figures & tables

Figure 1. Example of routing congestion formation in a placement–routing workflow. (a): multiple logic blocks are placed on the layout grid with interconnecting nets. (b): global routing paths overlap and compete for limited routing resources, creating localized routing congestion. (c): accumulated routing demand is visualized as a congestion map, where colors indicate congestion levels (low to high), and red regions highlight areas where routing demand exceeds available capacity.

Figure 2. Overview of VeriHGN graph construction. Starting from the original circuit design ( 1 ), we derive a hierarchical grid representation ( 2 ) for multi-level spatial structure, a netlist graph ( 3 ) for circuit connectivity, and a cell-to-grid relationship graph ( 4 ) for spatial assignment. These components are integrated into a unified heterogeneous graph ( 5 ), enabling joint structural and spatial message passing.

Figure 3. Relation-based message passing. Messages are propagated along different relation types (cell–net, grid–net, geom–cell, and cell–grid) using relation-specific MLPs, enabling information exchange across circuit components and spatial grids.

Figure 4. Hierarchical grid representation learning. Grid features are aggregated from fine to coarse levels and then propagated back from coarse to fine levels, enabling multi-scale spatial information exchange.

Figure 5. Embedding and readout. Embeddings from different node types (cell, geom, net, and grid) are concatenated and mapped through a readout layer to produce the final congestion heatmap.

Dataset	Tech.	#Designs	#Cells	#Nets	#Samples
ISPD 2015	–	20	100K–1.2M	100K–1.3M	533
CircuitNet-N28	28nm	10	35K–1.5M	38K–1.6M	$\sim$ 3K
CircuitNet-N14	14nm	8	35K–1.5M	38K–1.6M	$\sim$ 2K

Table 1. Summary of datasets used in our experiments.

Dataset	Model	Cell-level					Grid-level
Dataset	Model	MAE $\downarrow$	RMSE $\downarrow$	Pearson $\uparrow$	Spearman $\uparrow$	Kendall $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	Pearson $\uparrow$	Spearman $\uparrow$	Kendall $\uparrow$
ISPD2015	GCN	0.041	0.047	0.347	0.398	0.321	0.038	0.049	0.299	0.273	0.163
	GAT	0.039	0.045	0.361	0.385	0.337	0.036	0.046	0.304	0.273	0.179
	CircuitGNN	0.034	0.040	0.598	0.322	0.217	0.042	0.049	0.364	0.162	0.134
	MIHC	0.029	0.034	0.687	0.689	0.447	0.032	0.039	0.503	0.271	0.227
	ST-FPN	0.039	0.043	0.533	0.332	0.290	0.037	0.041	0.483	0.375	0.208

Table 2. Overall comparison of cell-level and grid-level congestion prediction performance.

	Cell-level			Grid-level
Remove Variant	MAE $\downarrow$	Spear. $\uparrow$	Kend. $\uparrow$	MAE $\downarrow$	Spear. $\uparrow$	Kend. $\uparrow$
None	0.037	0.548	0.414	0.034	0.401	0.308
Hierarchical Grid	0.039	0.511	0.383	0.038	0.342	0.261
Grid-Net MP	0.040	0.503	0.371	0.037	0.356	0.274
Geom. Cell–Cell MP	0.038	0.527	0.396	0.035	0.381	0.290
Gated Aggregation	0.038	0.531	0.399	0.035	0.387	0.295

Table 3. Ablation study on CircuitNet-N28. "None" denotes the complete VeriHGN model. Each row removes or replaces one component.

Figure 6. Sensitivity of VeriHGN to key hyperparameters on CircuitNet-N28: (a) number of message-passing layers

L

, (b) hidden dimension

d

, and (c) number of hierarchical grid levels

K

. Circles highlight the optimal configuration (

L=3

d=128

K=2

Train $\to$ Test	Model	MAE $\downarrow$	Pears. $\uparrow$	Spear. $\uparrow$	Kend. $\uparrow$	$\Delta\rho_{s}$
N14 $\to$ N14	MIHC	0.036	0.524	0.512	0.447	–
N14 $\to$ N14	VeriHGN	0.038	0.543	0.513	0.461	–
N28 $\to$ N28	MIHC	0.036	0.661	0.522	0.396	–
N28 $\to$ N28	VeriHGN	0.037	0.663	0.548	0.414	–
N28 $\to$ N14	MIHC	0.062	0.198	0.168	0.114	32.8%
N28 $\to$ N14	VeriHGN	0.056	0.261	0.224	0.159	43.7%

Table 4. Cross-design generalization (cell-level).

\Delta\rho_{s}

denotes the relative Spearman retention under transfer:

\rho_{s}^{\text{transfer}}/\rho_{s}^{\text{in-domain}}

Transfer	0%	10%	30%	50%	70%	90%	Non-trans.
N28 $\rightarrow$ N14	0.224	0.330	0.400	0.490	0.500	0.510	0.513
N14 $\rightarrow$ N28	0.258	0.353	0.421	0.516	0.538	0.544	0.548

Table 5. Few-shot fine-tuning sensitivity under cross-design transfer. The reported metric is cell-level Spearman correlation.

Model	Dataset	GC (S,M,L) (s)	Train (min)	Epoch (s)	Inf. (s)	Mem. (GB)
CircuitGNN	ISPD2015	(8.0, 180.3, 286.4)	41.3	17.0	9.0	14.0
	N14	(2.5, 160.7, 303.3)	180.3	18.0	13.3	21.0
	N28	(2.7, 177.9, 300.0)	161.7	15.0	11.3	17.0
MIHC	ISPD2015	(2.8, 215.4, 678.6)	97.6	29.1	14.6	18.45
	N14	(3.9, 283.5, 684.0)	928.6	300.2	7.3	28.56
	N28	(3.7, 271.5, 584.0)	842.9	283.6	26.0	38.56

Table 6. Runtime and memory comparison across datasets.

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HGRP: Heterogeneous Graph Neural Network for Routability Prediction

Yule Sheng, Yue Yuan, Shan Shen, Daying Sun

Nanjing University of Science and Technology, Nanjing, China

Electronic Design Automation Heterogeneous GNNs

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Routability prediction enables rapid evaluation of placement quality without routing, providing effective feedback for routability-driven placement optimization. Recent machine learning methods have achieved efficient routability prediction through data-driven approach. However, their prediction performance highly depends on the capability of input representations to capture essential circuit information. To address the limitations of existing circuit representations in simultaneously preserving logical topology, physical layout and routing resource information, this paper proposes HGRP, a heterogeneous graph neural network for routability prediction. HGRP models the cells, nets, and routing grids as distinct types of nodes and explicitly represents topological connectivity, spatial mapping, and grid adjacency, thereby constructing a heterogeneous graph representation that preserves multi-level circuit semantics. Based on the representation, a heterogeneous message passing mechanism is developed to enable information interaction and feature fusion among distinct types of nodes, effectively learning the complex correlations between circuit structures and routing behaviors. Experimental results on the CircuitNet dataset show that HGRP improves F1-score by 18.69% relative improvements compared with the state-of-the-art in the congestion prediction task. The source code is publicly available at https://github.com/ShenShan123/HGPR.

Abstract

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