SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

Kanishka Gunawardana; Sanka Peeris; Kavishka Rambukwella; Thamish Wanduragala; Saadia Jameel; Roshan Ragel; Isuru Nawinne

cs.ARMar 12, 2026

SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

Authors: Kanishka Gunawardana, Sanka Peeris, Kavishka Rambukwella, Thamish Wanduragala, Saadia Jameel, Roshan Ragel, Isuru Nawinne

Organizations: Department of Computer Engineering, Faculty of Engineering, University of Peradeniya, Peradeniya 20400, Sri Lanka

Abstract

Spiking Neural Networks (SNNs) have gained significant attention in edge computing due to their low power consumption and computational efficiency. However, existing implementations either use conventional System on Chip (SoC) architectures that suffer from memory-processor bottlenecks, or large-scale neuromorphic hardware that is inefficient and wasteful for small-scale SNN applications. This work presents SNAP-V, a RISC-V-based neuromorphic SoC with two accelerator variants: Cerebra-S (bus-based) and Cerebra-H (Network-on-Chip (NoC)-based) which are optimized for small-scale SNN inference, integrating a RISC-V core for management tasks, with both accelerators featuring parallel processing nodes and distributed memory. Experimental results show close agreement between software and hardware inference, with an average accuracy deviation of 2.62% across multiple network configurations, and an average synaptic energy of 1.05 pJ per synaptic operation (SOP) in 45 nm CMOS technology. These results show that the proposed solution enables accurate, energy-efficient SNN inference suitable for real-time edge applications.

Figures & tables

Fig. 1: High Level Overview of SNAP-V SOC. The architecture integrates a MainCore for general-purpose tasks and a SpikeCore for accelerator orchestration via the RoCC interface. The neuromorphic subsystem (Cerebra-H) communicates with the SoC through a dedicated Blackbox Module containing encoding/decoding hardware and an accelerator controller.

Fig. 2: Accelerator Design of Cerebra-S. The architecture consists of a tiled array of 1024 physical neurons connected to a shared neuron interconnect via a global tagged bus. Each individual neuron tile contains an accumulator unit for synaptic integration, a potential decay unit, and a potential adder unit for threshold evaluation and spike generation.

Fig. 3: Accelerator Design of Cerebra-H. The clustered neuromorphic architecture employs a hierarchical Network-on-Chip (NoC) topology. Lower-layer routers (L1) connect groups of four neuron clusters (NC0-NC31), which are further aggregated by a central upper-layer router (L2) to facilitate parallel spike communication and reduce global routing overhead.

Fig. 4: Neuron Microarchitecture. The internal datapath of a single configurable Leaky Integrate-and-Fire (LIF) neuron. It includes a finite-state machine control logic block, an accumulator unit for integrating incoming 32-bit synaptic weights, a potential decay unit utilizing arithmetic right-shifts, and a potential adder unit that evaluates membrane thresholds to generate spike outputs.

Fig. 5: Functional Block Diagram of a Cluster. The internal organization of a single 32-neuron cluster illustrating the dual communication paths. The cluster controller manages configuration packets, while the incoming forwarder and outgoing encoder handle the routing and serialization of 11-bit spike packets to and from the local neuron bank.

Specification	Description
Concurrent Access Ports	Four per-cluster request queues (depth eight)
Memory Interface	Single-port shared memory with asynchronous read; row width equals 32 times the neurons per cluster (default 1024 bits)
Buffer Management	Per-queue occupancy is exposed for flow control
Arbitration Logic	Fixed priority (port 0 over 1 over 2 over 3) with one-hot grant
Weight Distribution	Four parallel output lanes; only the granted lane carries data, accompanied by a per-lane valid indicator
Pipeline/Latency	One cycle from arbitration to a valid output lane; zero additional cycles for memory read (combinational)

TABLE I: Weight resolver specifications and capabilities

Aspect	Data/Control Packet Path	Spike Packet Path
Primary Use	System boot-up and configuration	Real-time spike communication
Buffering	No internal buffers	FIFO buffers at each port
Routing Method	Address-based routing	Predefined port mappings
Flow Control	Valid/ready handshake	FIFO status flags
Latency	Three cycles per hop	Multi-cycle pipelined
Traffic Pattern	Sparse, bursty	High-throughput

TABLE II: Comparison of dual data paths in router design

Design	Tech Node	Area ( $mm^{2}$ )	Neuron Count	Freq. (MHz)	Power (W)	Energy (pJ/SOP)
SNAP-V (This Work)	45 nm CMOS	25.74	1024	96.24	0.5001	1.05
ODIN [ 25 ]	28 nm FD-SOI	0.086	256	75–100	–	12.7
OpenSpike [ 47 ]	130 nm	33.3	1,024	40	$\approx$ 0.225	–
TrueNorth [ 22 ]	28 nm CMOS	430	1,000,000	0.001	0.065	26.0
Loihi 1 [ 4 ]	14 nm FinFET	60	131,000	-	-	23.6
Loihi 2 [ 21 ]	Intel 4 (7 nm)	31	1,000,000	$\approx$ 1000	1.55	10.1–11.5

TABLE III: Comparison of Cerebra-H with representative neuromorphic systems including Area and Frequency metrics

Hidden Layer	Software	Hardware	Diff.	Samples
Neurons	Acc. (%)	Acc. (%)	(%)	(Exp.)
16	92.83	87.11	$-5.72$	16
32	95.14	92.32	$-2.82$	16
64	96.45	93.94	$-2.52$	16
128	97.13	95.72	$-1.42$	16
256	97.32	96.69	$-0.63$	16

TABLE IV: Average functional accuracy across hidden layer sizes and all temporal configurations

Subsystem	Power (mW)	Percentage (%)
Weight Memory	479.95	95.97
Neuron Clusters	17.00	3.40
Spike Packet Paths	2.44	0.49
Data/Control Packet Paths	0.72	0.14
Total System Power	500.10	100.00

TABLE V: Component level power breakdown for the complete Cerebra-H

Neuromorphic Computing

Neuromorphic computing uses brain-inspired, event-driven algorithms and hardware to process information with low power and latency.

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An FPGA-Based SoC Architecture with a RISC-V Controller for Energy-Efficient Temporal-Coding Spiking Neural Networks

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Spiking Neural Networks (SNNs) offer high energy efficiency and event-driven computation, ideal for low-power edge AI. Their hardware implementation on FPGAs, however, faces challenges due to heavy computation, large memory use, and limited flexibility. This paper proposes a compact System-on-Chip (SoC) architecture for temporal-coding SNNs, integrating a RISC-V controller with an event-driven SNN core. It replaces multipliers with bitwise operations using binarized weights, includes a spike-time sorter for active spikes, and skips noninformative events to reduce computation. The architecture runs fully on a Xilinx Artix-7 FPGA, achieving up to 16x memory reduction for weights and lowering computational overhead and latency, with 97.0% accuracy on MNIST and 88.3% on FashionMNIST. This self-contained design provides an efficient, scalable platform for real-time neuromorphic inference at the edge.

Abstract

Neuromorphic Computing

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