cs.LGMar 12, 2026

Geometry-Aware Probabilistic Circuits via Voronoi Tessellations

Authors: Sahil Sidheekh, Sriraam Natarajan

Organizations: The University of Texas at Dallas, Richardson, TX, USA.

Abstract

Probabilistic circuits (PCs) enable exact and tractable inference but employ data independent mixture weights that limit their ability to capture local geometry of the data manifold. We propose Voronoi tessellations (VT) as a natural way to incorporate geometric structure directly into the sum nodes of a PC. However, naïvely introducing such structure breaks tractability. We formalize this incompatibility and develop two complementary solutions: (1) an approximate inference framework that provides guaranteed lower and upper bounds for inference, and (2) a structural condition for VT under which exact tractable inference is recovered. Finally, we introduce a differentiable relaxation for VT that enables gradient-based learning and empirically validate the resulting approach on standard density estimation tasks.

Figures & tables

Appendix figures & tables1 asset

Supplementary material from the paper’s appendix.

Appendix

Explore similar work

CardsList
  1. Neural Approximation of Generalized Voronoi Diagrams

    Mar 27, 2026Panagiotis Rigas, George Ioannakis, Ioannis EmirisNeural Surrogate ModelingImplicit Neural Representations

  2. PeTeR: Post-Training Robustification of Probabilistic Circuits

    Jul 8, 2026Adrian Ciotinga, Yeming Dai, YooJung ChoiDistribution Shift RobustnessProbabilistic Circuits

  3. Predictive variational inference: Learn the predictively optimal posterior distribution

    Oct 18, 2024Jinlin Lai, Antonio Linero, Yuling YaoModel MisspecificationVariational Inference