OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM

Yiqi Zhou; Yue Yuan; Yikai Wang; Bohao Liu; Qinxin Mei; Zhuohua Liu; Shan Shen; Wei Xing

cs.LGMar 13, 2026

OpenACMv2: An Accuracy-Constrained Co-Optimization Framework for Approximate DCiM

Authors: Yiqi Zhou, Yue Yuan, Yikai Wang, Bohao Liu, Qinxin Mei, Zhuohua Liu, Shan Shen, Wei Xing,

Organizations: Nanjing University of Science and Technology, China · Shenzhen University, China · Beihang University, China · University of Sheffield, UK ·

Abstract

Digital Compute-in-Memory (DCiM) accelerates neural networks by reducing data movement. Approximate DCiM can further improve power-performance-area (PPA), but demands accuracy-constrained co-optimization across coupled architecture and transistor-level choices. Building on OpenYield, we introduce Accuracy-Constrained Co-Optimization (ACCO) and present OpenACMv2, an open framework that operationalizes ACCO via two-level optimization: (1) accuracy-constrained architecture search of compressor combinations and SRAM macro parameters, driven by a fast GNN-based surrogate for PPA and error; and (2) variation- and PVT-aware transistor sizing for standard cells and SRAM bitcells using Monte Carlo. By decoupling ACCO into architecture-level exploration and circuit-level sizing, OpenACMv2 integrates classic single- and multi-objective optimizers to deliver strong PPA-accuracy tradeoffs and robust convergence. The workflow is compatible with FreePDK45 and OpenROAD, supporting reproducible evaluation and easy adoption. Experiments show that the proposed two-level ACCO framework achieves most of its accuracy-constrained efficiency gain at Level-1 through architecture exploration, delivering roughly 50%+ PDP reduction, while Level-2 transistor-level optimization provides a further single-digit PDP improvement while preserving accuracy, enabling rapid "what-if" exploration for approximate DCiM. The framework is available on GitHub (https://github.com/ShenShan123/OpenACM).

Figures & tables

Figure 1. The overall structure of OpenACM, an approximate DCiM compiler, provides an end-to-end DCiM flow. A processing element contains a multiplier and an SRAM macro.

Figure 2. OpenACMv2 ACCO workflow: Level-1 architecture search guided by PEA-GNN, followed by Level-2 variation/PVT-aware transistor sizing. Foundation circuit generators are OpenACM and OpenYield.

Figure 3. The structure of the 8-bit approximate multiplier. It consists of 3 stages: (i) partial-product generation, (ii) a configurable reduction tree with approximate compressors on selected columns, and (iii) a final carry-propagate adder.

Figure 4. PEA-GNN: stage-wise graph, node-feature fusion, and regression.

Metric	8-bit			16-bit
Metric	MSE ( $\times 10^{-4}$ )	MRE (%)	R 2	MSE ( $\times 10^{-4}$ )	MRE (%)	R 2
MRED	0.52	2.17	0.998	2.94	4.73	0.977
NMED	9.25	1.84	0.996	2.66	2.30	0.959
Delay	6.52	0.03	0.969	7.39	0.22	0.917
Area	1.77	0.11	0.991	3.65	0.12	0.978
Power	2.34	0.30	0.989	0.86	0.25	0.968

Table 1. Inference accuracy and runtime comparison of 8-bit and 16-bit PEA-GNN models.

Figure 7. Transistor-level Pareto frontiers: across optimizers on the Sabetz compressor ( Sabetzadeh et al., 2019 ) (left); across compressors using MOEA/D (right). Rhomboids are reference points.

Compute-in-Memory

Compute-in-memory (CIM) performs computation within or beside memory arrays to reduce data movement and accelerate AI workloads.

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OpenOpt: An Open-Source SRAM Optimizer Based on Equivalent Circuit Model

Yikai Wang, Yiheng Wu, Can Wang, Bohao Liu+4

Nanjing University of Science and Technology, Nanjing, 210094, China · Shenzhen University,Shenzhen, 518060, China · Beihang University, Beijing, 100191, China

Electronic Design Automation

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This paper proposes a co-optimization framework that jointly optimizes SRAM architecture and transistor sizing using equivalent circuit models. The framework simplifies inactive SRAM cells into equivalent RC loads and static power models, achieving up to 61.4

\times

simulation speedup while maintaining high fidelity (read/write delay error

<

0.22%, power error

<

1.68%). A joint search space encompassing architecture parameters and device sizing integrates seven algorithms including SA, PSO, Bayesian Optimization variants, and multi-objective evolutionary algorithms. Based on FreePDK45, ablation experiments confirm complementary gains from architecture selection and transistor sizing. Among all algorithms, MOEA/D achieves the best Figure of Merit (8.2721), yielding 6.2% improvement in SNM, 73.6% reduction in area, and 42.3% reduction in peak power. The framework is publicly available at https://github.com/W1Y1K1/OpenOpt.

Abstract

Compute-in-Memory

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