SPARQ: Spiking Early-Exit Neural Networks for Energy-Efficient Edge AI

Parth Patne; Mahdi Taheri; Ali Mahani; Maksim Jenihhin; Reza Mahani; Christian Herglotz

cs.LGMar 15, 2026

SPARQ: Spiking Early-Exit Neural Networks for Energy-Efficient Edge AI

Authors: Parth Patne, Mahdi Taheri, Ali Mahani, Maksim Jenihhin, Reza Mahani, Christian Herglotz

Organizations: Brandenburg Technical University, Cottbus, Germany · Tallinn University of Technology, Tallinn, Estonia · Shahid Bahonar University of Kerman, Iran · York University, Toronto, Canada ·

Abstract

Spiking neural networks (SNNs) offer inherent energy efficiency due to their event-driven computation model, making them promising for edge AI deployment. However, their practical adoption is limited by the computational overhead of deep architectures and the absence of input-adaptive control. This work presents SPARQ, a unified framework that integrates spiking computation, quantization-aware training, and reinforcement learning-guided early exits for efficient and adaptive inference. Evaluations across MLP, LeNet, and AlexNet architectures demonstrated that the proposed Quantised Dynamic SNNs (QDSNN) consistently outperform conventional SNNs and QSNNs, achieving up to 5.15% higher accuracy over QSNNs, over 330 times lower system energy compared to baseline SNNs, and over 90 percent fewer synaptic operations across different datasets. These results validate SPARQ as a hardware-friendly, energy-efficient solution for real-time AI at the edge.

Figures & tables

Model Variant	Dataset	Acc. (%)	Synaptic Ops (M)
5-Layer MLP
MLP	MNIST	98.02	41.16
Dynamic MLP	MNIST	98.72	32.22
SNN (T=32)	MNIST	95.00	65.50
QSNN (T=4)	MNIST	94.50	50.10
QDSNN (Cfg:0.2/0.4)	MNIST	95.50	22.30

Table 1: Accuracy and synaptic operations across all models. ANN ops are MACs; SNN ops are ACs. A detailed LIF and total operation breakdown for AlexNet is provided in Table 3 .

5-Layer MLP (MNIST)
Arch.	Variant	Acc.	Time	Power	Energy
		(%)	(ms)	(W)	(mJ)
	SNN (T=32)	95.00	539.0	0.080	43.10
	QSNN (T=4)	94.50	420.0	0.005	2.10
	QDSNN (0.2/0.4)	95.50	105.0	0.009	0.95
	QDSNN (0.6/0.7)	97.80	83.0	0.012	0.99

Table 2: SNN, QSNN, and QDSNN comparison. Energy includes memory access;

P=E/t

Model	Synaptic Ops	LIF Ops	Total Ops
ANN	200.52M MAC	–	200.52M
SNN (T=32)	26.06M AC	11.53M	37.59M
QSNN (T=4)	0.46M AC	1.44M	1.90M
QDSNN	0.27M AC	$\leq$ 7.37M	$\leq$ 7.64M

Table 3: Operation breakdown for AlexNet on CIFAR-10. QDSNN values are upper-bounds (

T

=32, full pass); actual ops are lower due to early exits.

Model	$E_{\text{syn}}$	$E_{\text{LIF}}$	$E_{\text{comp}}$	compute reduction
ANN	922.4 $\mu$ J	–	922.4 $\mu$ J	1 $\times$
SNN (T=32)	0.78 $\mu$ J	5.77 $\mu$ J	6.55 $\mu$ J	141 $\times$
QSNN (T=4)	0.014 $\mu$ J	0.72 $\mu$ J	0.73 $\mu$ J	1264 $\times$
QDSNN	0.008 $\mu$ J	$\leq$ 3.69 $\mu$ J	$\leq$ 3.70 $\mu$ J	$\geq$ 249 $\times$

Table 4: Computational energy for AlexNet on CIFAR-10 (arithmetic only; system energy in Table 2 ). QDSNN upper-bounds assume

T

=32.

Figure 1: AlexNet Operation Counts comparison across model variants.

Figure 2: Class distribution across exits for QDSNN (Cfg:0.6/0.7).

Spiking Neural Networks

Spiking neural networks process information through discrete, time-dependent neural events, aiming for efficient computation and biologically inspired learning.

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L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma

Centre for Advanced Electronics, Indian Institute of Technology Indore, Simrol 453552, Indore, India · Dept. of Electrical Engineering, Indian Institute of Technology Indore, Simrol 453552, Indore, India

Efficient Neural Network Inference Spiking Neural Networks FPGA-Based Neural Network Acceleration Edge Inference

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Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.

Abstract

Spiking Neural Networks

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