KANtize: Exploring Low-bit Quantization of Kolmogorov-Arnold Networks for Efficient Inference

Sohaib Errabii; Olivier Sentieys; Marcello Traiola

cs.ARMar 18, 2026

KANtize: Exploring Low-bit Quantization of Kolmogorov-Arnold Networks for Efficient Inference

Authors: Sohaib Errabii, Olivier Sentieys, Marcello Traiola

Organizations: Univ Rennes, Inria, CNRS, IRISA, Rennes, France

Abstract

Kolmogorov-Arnold Networks (KANs) have gained attention for their potential to outperform Multi-Layer Perceptrons (MLPs) in terms of parameter efficiency and interpretability. Unlike traditional MLPs, KANs use learnable non-linear activation functions, typically spline functions, expressed as linear combinations of basis splines (B-splines). B-spline coefficients serve as the model's learnable parameters. However, evaluating these spline functions increases computational complexity during inference. Conventional quantization reduces this complexity by lowering the numerical precision of parameters and activations. However, the impact of quantization on KANs, and especially its effectiveness in reducing computational complexity, is largely unexplored, particularly for quantization levels below 8 bits. The study investigates the impact of low-bit quantization on KANs and its impact on computational complexity and hardware efficiency. Results show that B-splines can be quantized to 2-3 bits with negligible loss in accuracy, significantly reducing computational complexity. Hence, we investigate the potential of using low-bit quantized precomputed tables as a replacement for the recursive B-spline algorithm. This approach aims to further reduce the computational complexity of KANs and enhance hardware efficiency while maintaining accuracy. For example, ResKAN18 achieves a 50x reduction in BitOps without loss of accuracy using low-bit-quantized B-spline tables. Additionally, precomputed 8-bit lookup tables improve GPU inference speedup by up to 2.9x, while on FPGA-based systolic-array accelerators, reducing B-spline table precision from 8 to 3 bits cuts resource usage by 36%, increases clock frequency by 50%, and enhances speedup by 1.24x. On a 28nm FD-SOI ASIC, reducing the B-spline bit-width from 16 to 3 bits achieves 72% area reduction and 50% higher maximum frequency.

Figures & tables

Fig. 1 : A single layer of dimensions [2, 2] for MLP (a) and KAN (b). Details of spline computation as a linear combination of B-splines

Fig. 2 : B-Spline basis for

G=3

P=3

and

G+2P+1=10

grid points

[t_{0},\dots,t_{9}]

Fig. 3 : The compute graph of a KAN layer $l$ consists of B-spline evaluation followed by a standard matrix multiplication.

Fig. 4 : Cox-de Boor evaluation triangle for B-splines

b_{3,3}

and

b_{4,3}

of degree

P=3

. Each row corresponds to the recursive computations of

b_{i,P}(x)

from

b_{i,P-1}(x)

and

b_{i+1,P-1}(x)

. The number of required B-splines in every row decreases linearly with

P

, leading to the total number of operations in Table I .

	MLP	KAN
Matrix Multiply	$MN_{out}N_{in}$	$MN_{out}N_{in}(G+P)$
Non Linearity (B-splines)	_	$4MN_{in}\left(P(G+2P)-\frac{P(P-1)}{2}\right)$

TABLE I : Number of multiplications (MULs) of

[N_{in},N_{out}]

MLP and KAN layers with batch size

M

Fig. 5 : Only half the values of one B-spline need to be stored (e.g., half of

b_{3,3}

, colored in black), and the other B-splines can be evaluated by translating the input and using symmetry.

Fig. 6 : Tabulation of the canonical B-spline

B_{0,3}(x)

: only the first half is stored with

2^{k}

entries per knot interval

[t_{i},t_{i+1}]

Fig. 7 : Naive tabulation example with

G=15

k=4

: uniform quantization to

2^{k}

levels wastes entries in zero regions, capturing only 5 of 16 entries for the B-spline.

Fig. 8 : Example of a learned spline in the single-layer KAN

[784,10]

for different

G

values. The legend shows the number of bits used for input quantization.

Model	Type	Dataset	Dimensions	Params
KANMLP1	KAN	MNIST	$[784,10]$	47 K
KANMLP2	KAN	MNIST	$[784,64,10]$	305 K
LeKAN	ConvKAN	MNIST	$[1,6,16]$ ( $5{\times}5$ )	39 K
CNN3	ConvKAN	CIFAR-10	$[3,32,64,128]$	560 K
CNN4	ConvKAN	CIFAR-10	$[3,32,64,128,512]$	4.1 M
ResKAN18	ConvKAN	CIFAR-10	ResNet18	67 M

TABLE II : Models used in the evaluation (

P\!=\!3

G\!=\!3

). Dimensions denote layer widths for KAN models and channel count for ConvKAN models (

3{\times}3

kernels unless noted).

Panel of Figure 11 — Fig. 9 : Accuracy vs BitOps trade-off results of KAN quantization. Single component graphs (a,b,c,g,h,i) report results when quantizing only one component of the KAN layer at a time, i.e., $W^{(l)}$ , $A^{(l)}$ , and $B^{(l)}$ . For different components, different line styles are used, and for different bit widths, different shapes. All component graphs (d,e,f,j,k,l) show the Pareto front of results obtained through quantizing multiple components of the KAN layer at the same time. The bit-widths of $W^{(l)}$ , $A^{(l)}$ , and $B^{(l)}$ are encoded by marker colors, sizes, and shapes, respectively.

Panel of Figure 12 — Fig. 10 : Accuracy vs LUT Memory trade-off for B-spline tabulation with 8-bit weights $W^{(l)}$ . The graphs show the Pareto front of accuracy versus LUT memory cost for different bit-widths of $A^{(l)}$ (marker size) and stored values $B^{(l)}$ (marker shape).

Panel of Figure 13 — Fig. 11 : Accuracy vs BitOPs trade-off for B-spline tabulation combined with quantization. By replacing Cox-de Boor evaluation with a LUT, the B-spline computational cost is eliminated, leaving only the matrix multiplication. The bit-width of $W^{(l)}$ is encoded by marker color, that of $A^{(l)}$ (LUT addressing) by marker size, and that of $B^{(l)}$ (LUT stored values) by marker shape.

Model	$G$	Baseline	BSP %	BSP Tab.	Speedup
		(ms)		(ms)
MNIST
KANMLP1	$3$	$13.9$	$96$	$4.8$	$2.87\times$
KANMLP1	$5$	$17.6$	$97$	$5.2$	$3.36\times$
KANMLP2	$3$	$15.2$	$97$	$5.4$	$2.83\times$
KANMLP2	$5$	$19.3$	$98$	$5.9$	$3.29\times$

TABLE III : GPU time (ms) on RTX3090 for the full test set (10 000 samples) with 8-bit B-spline tabulation (256 entries), measured with torch.profiler .

P\!=\!3

for all models.

B	Array	Slice LUTs		Slices		CC	Time
(bits)	size	(%)		(%)			(ms)
8	$15\times 15$	113.7k/	85%	32.1k/	96%	5 206k	183.0
7	$16\times 16$	124.9k/	93%	33.3k/	100%	4 219k	156.4
5	$18\times 18$	119.7k/	89%	32.8k/	98%	3 618k	162.1
4	$19\times 19$	114.4k/	86%	33.2k/	99%	3 286k	157.9
3	$20\times 20$	115.2k/	86%	32.6k/	98%	2 969k	147.0

TABLE IV : FPGA resource utilization and average measured inference time over 5 MNIST-shaped MLP workloads

[784,n,10]

with

n\in\{32,64,128,192,256\}

(batch = 10 000) with varying B-spline table bit-width (

G\!=\!5

P\!=\!3

, 50 MHz).

B	Slice LUTs		Max Freq
(bits)	(%)		(MHz)
8 †	—		—
7	124.9k /	93%	50
6	118.1k /	88%	60
5	97.9k /	73%	70
4	85.2k /	64%	75

TABLE V : Maximum clock frequency for a

16\times 16

KAN-SAs systolic array with varying B-spline table bit-width on FPGA (

W\!=\!8

G\!=\!5

P\!=\!3

Panel of Figure 17 — Fig. 12 : Accuracy vs Spline Table Memory trade-off for spline tabulation. The graphs show the Pareto front of accuracy versus total spline table memory cost for different bit-widths of $A^{(l)}$ (marker size) and stored value precision $h$ (marker shape).

B	W	Area @ 1 GHz	Max frequency
(bits)	(bits)	( $\mu m^{2}$ )	(MHz)	Area ( $\mu m^{2}$ )
16	16	1 425 590 †	833	1 479 594
8	8	574 102	1 111	596 850
7	8	541 978	1 176	581 353
6	8	515 865	1 176	532 536
5	8	470 712	1 250	489 225

TABLE VI : ASIC synthesis results for a

16\times 16

KAN-SAs systolic array with varying B-spline and weight precision (ST 28nm FD-SOI,

G\!=\!5

P\!=\!3

Model	$G$	Baseline	Spline Tab.	Speedup
		(ms)	(ms)
MNIST
KANMLP1	$3$	$13.9$	$1.9$	$7.3\times$
KANMLP1	$5$	$17.6$	$1.9$	$9.1\times$
KANMLP2	$3$	$15.2$	$6.4$	$2.4\times$
KANMLP2	$5$	$19.3$	$6.4$	$3.0\times$

TABLE VII : GPU time (ms) on RTX3090 for spline tabulation with 256 entries and 32-bit values, measured with torch.profiler .

P\!=\!3

for all models.

Fig. 13 : CUDA kernel time breakdown for baseline (Cox-de Boor) vs spline tabulation on CNN3, CNN4, and ResKAN18 (

G\!=\!3

P\!=\!3

, RTX3090).

Fig. 14 : Estimated FPGA LUT cost of spline tabulation [ 10 ] for the models studied in this paper. The dashed red line indicates the capacity of a Virtex UltraScale+ FPGA. Horizontal green lines report KAN-SAs systolic array [ 8 ] configurations, labeled by B-spline coefficient precision

B

, weight precision

W

, activation precision

A

, and array dimensions.

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