SOL-ExecBench: Speed-of-Light Benchmarking for Real-World GPU Kernels Against Hardware Limits
Organizations: NVIDIA
Abstract
As agentic AI systems become increasingly capable of generating and optimizing GPU kernels, progress is constrained by benchmarks that reward speedup over software baselines rather than proximity to hardware-efficient execution. We present SOL-ExecBench, a benchmark of 235 CUDA kernel optimization problems extracted from 124 production and emerging AI models spanning language, diffusion, vision, audio, video, and hybrid architectures, targeting NVIDIA Blackwell GPUs. The benchmark covers forward and backward workloads across BF16, FP8, and NVFP4, including kernels whose best performance is expected to rely on Blackwell-specific capabilities. Unlike prior benchmarks that evaluate kernels primarily relative to software implementations, SOL-ExecBench measures performance against analytically derived Speed-of-Light (SOL) bounds computed by SOLAR, our pipeline for deriving hardware-grounded SOL bounds, yielding a fixed target for hardware-efficient optimization. We report a SOL Score that quantifies how much of the gap between a release-defined scoring baseline and the hardware SOL bound a candidate kernel closes. To support robust evaluation of agentic optimizers, we additionally provide a sandboxed harness with GPU clock locking, L2 cache clearing, isolated subprocess execution, and static analysis based checks against common reward-hacking strategies. SOL-ExecBench reframes GPU kernel benchmarking from beating a mutable software baseline to closing the remaining gap to hardware Speed-of-Light.
Figures & tables
| Benchmark | Problems | Source | Metric | Precision | Target | Train |
|---|---|---|---|---|---|---|
| HW | ||||||
| KernelBench | 270 | Curated + models | FP32/FP16/BF16 | Any | × | |
| FlashInfer-Bench | 26 | Inference traces | FP16/BF16/FP8 | BW | × | |
| BackendBench | 271 | PyTorch OpInfo | Speedup | FP32/FP16/BF16 | Any | Partial |
| TritonBench | 184 | GitHub repos | Correctness+ | FP32/FP16/BF16 | Any | × |
| ComputeEval | 232 | Synthetic | pass@1 | FP32/FP16 | Any | × |
| Cat. | Description | # | Precision | Examples |
|---|---|---|---|---|
| L1 | Single-operation kernels extracted from real models; building blocks of neural network computation | 94 | BF16 / FP32 | GQA, RMSNorm, SwiGLU, RoPE |
| L2 | Multi-operation fused kernels representing complete computational blocks; 3–10 more complex than L1 | 82 | BF16 / FP32 | Decoder layers, MoE dispatch, SSM chunk scan, cross-attention |
| Quant | Kernels with explicit low-precision compute extracted from quantized models. 18 use FP8 blockwise scaling, 15 use NVFP4 16-element block scaling | 33 | FP8 / NVFP4 | FP8 MLA projection, NVFP4 MoE expert, FP8 MoE gate |
| FIB | Standalone inference primitives from three production model families (Llama-3.1-8B, Qwen3-30B-A3B, DeepSeek-V3/R1) | 26 | BF16 / FP8 | Fused attention, FP8 MoE, RMSNorm |
| Total | 235 |
| Category | Exploit Description | Defense Mechanism |
|---|---|---|
| Concurrency | Thread Injection: Hiding work on unrecorded Python threads. | Thread count monitoring. |
| Stream Injection: Hiding work on unsynchronized CUDA streams. | Disabling multi-stream usage. | |
| JIT Forking: Abusing torch.jit.fork for parallel execution. | LLM-judge static analysis. | |
| State & Caching | Reuse Cached Output: Caching outputs based on data_ptr and returning them during timing. | Input cloning; custom memory allocator to prevent address caching; LLM-judge. |
| Lazy Evaluation: Returning FakeTensor s that only compute during eq validation. | Strict type checking ( type(t) is torch.Tensor ). | |
| One-time Correctness: Skipping math after the first successful validation pass. | Multiple correctness trials with randomized inputs |
GPU Kernel Optimization
GPU kernel optimization improves the speed and memory efficiency of computations by tailoring code to GPU hardware and workloads.
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