FluxEDA: A Unified Execution Infrastructure for Stateful Agentic EDA
Organizations: Zhejiang University, Hangzhou, China
Abstract
Large language models and autonomous agents are increasingly explored for EDA automation, but many existing integrations still rely on script-level or request-level interactions, which makes it difficult to preserve tool state and support iterative optimization in real production-oriented environments. In this work, we present FluxEDA, a unified and stateful infrastructure substrate for agentic EDA. FluxEDA introduces a managed gateway-based execution interface with structured request and response handling. It also maintains persistent backend instances. Together, these features allow upper-layer agents and programmable clients to interact with heterogeneous EDA tools through preserved runtime state, rather than through isolated shell invocations. We evaluate the framework using two representative commercial backend case studies: automated post-route timing ECO and standard-cell sub-library optimization. The results show that FluxEDA can support multi-step analysis and optimization over real tool contexts, including state reuse, rollback, and coordinated iterative execution. These findings suggest that a stateful and governed infrastructure layer is a practical foundation for agent-assisted EDA automation.
Figures & tables
| State | Setup WNS (ns) | Setup TNS (ns) | Setup Violating Paths | Hold WHS (ns) | Hold THS (ns) | Hold Violations |
|---|---|---|---|---|---|---|
| Baseline | -0.81 | -37.37 | 140 | -0.39 | -1.33 | 4 |
| Iteration 1 | -0.76 | -34.78 | 130 | -0.38 | -1.33 | 4 |
| Iteration 2 | -0.76 | -34.84 | 133 | -0.39 | -1.33 | 4 |
| Iteration 3 | -0.76 | -34.78 | 130 | +0.01 | 0.00 | 0 |
| State | Area ( ) | WNS (ns) | TNS (ns) | Viol. Paths | Used Cell Refs. ( vs. Base) | Used Cell Families. ( vs. Base) |
|---|---|---|---|---|---|---|
| Baseline | 14651.55 | -0.246 | -20.996 | 122 | 149 (0.0%) | 51 (0.0%) |
| A-Run9 | 12530.89 | -1.114 | -186.934 | 237 | 22 (85.2%) | 20 (60.8%) |
| T-Run04 | 12748.21 | -0.791 | -97.780 | 228 | 23 (84.6%) | 20 (60.8%) |
| T-Run10 | 14580.79 | -0.385 | -41.803 | 181 | 30 (79.9%) | 20 (60.8%) |
| T-Run11 | 13659.95 | -0.448 | -40.306 | 157 | 36 (75.8%) | 23 (54.9%) |
Appendix figures & tables1 asset
Supplementary material from the paper’s appendix.
Appendix
| ID | Parent | Change | Decision Intent | Area ( ) | WNS (ns) | TNS (ns) | Viol. Paths |
|---|---|---|---|---|---|---|---|
| Baseline | – | full-library baseline | Reference upper bound with full library support | 14651.546 | -0.246 | -20.996 | 122 |
| A-Run1 | – | minimal textbook X1 seed | Test whether the smallest valid seed library can launch the flow | 14064.271 | -1.462 | -230.246 | 241 |
| A-Run2 | A-Run1 | add ND3/NR3 X1 | Check whether 3-input logic reduces depth under the minimal seed | 13901.532 | -1.339 | -217.843 | 241 |
| A-Run3 | A-Run2 | add AOI12/OAI12 X1 | Check whether compound gates further compress critical logic depth | 12985.748 | -1.301 | -208.113 | 244 |
| A-Run4 | A-Run3 | add AOI22/OAI22 X1 | Complete a basic compound-gate support set and probe the area minimum | 12732.037 | -1.145 | -195.882 | 244 |
| A-Run5 | A-Run4 | add OAI12 X2 | Test whether endpoint-side complex-gate resizing helps | 12763.372 | -1.179 | -190.739 | 244 |
Electronic Design Automation
Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.
See all 213 papers