Brain-inspired AI for Edge Intelligence: a systematic review

Yingchao Cheng; Meijia Wang; Zhifeng Hao; Rajkumar Buyya

cs.NEMar 19, 2026

Brain-inspired AI for Edge Intelligence: a systematic review

Authors: Yingchao Cheng, Meijia Wang, Zhifeng Hao, Rajkumar Buyya

Organizations: Guangdong Laboratory of Artificial Intelligence and Digital Economy (SZ), Shenzhen, 518107, China · Cloud Computing and Distributed Systems (CLOUDS) Lab, School of Computing and Information Systems, University of Melbourne, Melbourne, VIC 3010, Australia · College of Mathematics and Computer Science, Shantou University, Shantou, 515063, China

Abstract

While Spiking Neural Networks (SNNs) promise to circumvent the severe Size, Weight, and Power (SWaP) constraints of edge intelligence, the field currently faces a "Deployment Paradox" where theoretical energy gains are frequently negated by the inefficiencies of mapping asynchronous, event-driven dynamics onto traditional von Neumann substrates. Transcending the reductionism of algorithm-only reviews, this survey adopts a rigorous system-level hardware-software co-design perspective to examine the 2020-2025 trajectory, specifically targeting the "last mile" technologies - from quantization methodologies to hybrid architectures - that translate biological plausibility into silicon reality. We critically dissect the interplay between training complexity (the dichotomy of direct learning vs. conversion), the "memory wall" bottlenecking stateful neuronal updates, and the critical software gap in neuromorphic compilation toolchains. Finally, we envision a roadmap to reconcile the fundamental "Sync-Async Mismatch," proposing the development of a standardized Neuromorphic OS as the foundational layer for realizing a ubiquitous, energy-autonomous Green Cognitive Substrate.

Figures & tables

Fig. 1: Overview of the paradigm shift from Traditional DNNs to Spiking Neural Networks (SNNs). (Top) Data Representation: DNNs process redundant frame-based image sequences, whereas SNNs process sparse, asynchronous event streams represented in a spatiotemporal volume ( $x,y,t$ ). (Middle) Neuron Dynamics: Unlike static activation functions (e.g., Sigmoid) in DNNs, SNNs employ biologically plausible Leaky Integrate-and-Fire (LIF) neurons that integrate temporal information governed by differential equations. (Bottom) Energy Efficiency: The shift from dense MAC operations to event-driven Accumulate (AC) logic results in an ultra-low energy footprint, making SNNs highly suitable for edge intelligence.

Fig. 2: Hierarchical Organization of the Survey. The article is structured into four main pillars: Part I establishes the theoretical foundations and defines the “Deployment Paradox”; Part II explores the technical frontiers across algorithms, hardware, and toolchains (2020–2025); Part III examines real-world realization in key edge applications; and Part IV synthesizes challenges to propose a roadmap towards a unified Neuromorphic OS.

Fig. 3: Dataflow Contrast: Continuous vs. Event-Driven. (Left) DNN Dataflow: Relies on dense Matrix-Vector Multiplication (MAC), creating a continuous “Memory Wall” as weights are fetched unconditionally. (Right) SNN Dataflow: Utilizes a conditional trigger mechanism where memory access and computation occur only upon spike arrival. This sparsity-aware processing significantly reduces off-chip memory bandwidth requirements.

Feature	SNNs	DNNs
Neuron Model	Biologically inspired (e.g., LIF, Izhikevich); discrete spikes	Abstracted; continuous activation values (e.g., ReLU, sigmoid)
Information Encoding	Temporal patterns of spikes (rate, latency, phase, population)	Magnitude of activations
Computation	Event-driven, asynchronous, sparse; primarily Accumulate (AC) ops	Synchronous, dense; primarily Multiply-Accumulate (MAC) ops
Energy Efficiency	Potentially very high, especially on neuromorphic hardware	Generally lower, can be power-intensive
Temporal Processing	Intrinsic capability to process temporal data	Often requires recurrent architectures (RNNs, LSTMs)
Biological Plausibility	Higher; mimics neural dynamics and learning rules like STDP	Lower; learning (e.g., backpropagation) often not bio-plausible

TABLE I: Comparison of SNNs and DNNs

Fig. 4: Radar chart illustrating the multidimensional trade-offs between Neuromorphic SNNs and a traditional Edge DNN baseline. While the DNN maintains a marginal advantage in static accuracy, the SNN demonstrates superior performance in SWaP-constrained metrics—specifically Energy Efficiency, Sparsity, and Always-on Suitability. This architectural alignment identifies SNNs as the optimal candidate for resource-limited edge deployment despite the accuracy trade-off.

Fig. 5: Taxonomy of Brain-inspired Edge Intelligence. The survey is structured around four pillars: (1) Training Paradigms : Highlighting the shift from conversion to direct training algorithms like STBP and tdBN ; (2) Neuromorphic Hardware : Covering native digital chips, FPGA accelerators, and hybrid architectures like Tianjic ; (3) Co-design Strategies : Focusing on NAS and temporal quantization; (4) System & Applications : Emphasizing high-speed vision ( Vidar ) and edge-cloud orchestration.

Platform	Dev.	Key Features for Edge SNNs	Capacity	Learn.	Eff.	Scale	Edge Relevance	Ref.
Loihi 2	Intel	Programmable spiking neurons, dynamic synapses, async processing	$>$ 1 M	Yes	●	●	Robotics, AI control	[ 95 ]
Hala Point	Intel	System of 1,152 Loihi 2 chips, massive parallelism	1.15 B	Yes	◐	● +	Large-scale AI research	[ 118 ]
Darwin3	ZJU	Rack-scale system, specialized SNN ISA, DarwinOS support	$>$ 2 B	Yes	◐	● +	Brain simulation, AGI	[ 119 ]
NorthPole	IBM	In-memory computing, inference-only optimization	N/A	No	● +	N/A	Ultra-low-power AI	[ 101 ]
Akida 2	BrainChip	Event-based, IP for SoC integration, TENNs support	Scalable	Yes	● +	●	IoT, wearables, smart home	[ 120 ]
SpiNNaker2	Manch.	ARM cores, custom spike routing	$>$ 1 M/bd	Soft.	○	● +	Robotics, embedded sys.	[ 121 ]

TABLE II: Prominent Neuromorphic Hardware Platforms Relevant for Edge SNNs (2023-2025 Updates)

Framework (Developer)	Core Features & Purpose	Edge-Relevant Capabilities	Ref.
Hardware Mapping Toolchains
NeuMap (NUDT)	Mapping SNNs to multicore HW; Comm. pattern calculation; Meta-heuristic cluster-to-core mapping	Optimized for NoC latency and energy on multicore edge hardware	[ 138 ]
EdgeMap (SJTU)	Optimized mapping for edge; Streaming-based partitioning; Multi-objective optimization (NSGA-II)	Significant reduction in latency, energy, and comm. cost for edge deployment	[ 137 ]
Deep Learning & Deployment Frameworks
Lava (Intel)	Neuro-inspired app dev; Modular; Platform-agnostic; Supports deep learning (lava-dl)	Native deployment on Loihi chips; Optimized for energy/speed efficiency	[ 139 ]
SNNTorch (UCSC)	PyTorch-based training; Surrogate gradients; Temporal dynamics; GPU acceleration	Facilitates training of deep SNNs deployable on edge; Seamless PyTorch integration	[ 23 ]

TABLE III: Selected SNN Software Frameworks and Mapping Toolchains (2020–2025)

Fig. 6: Proposed SNN-based Cloud-Edge Collaboration Framework. The cloud server hosts a complex Teacher ANN to guide lightweight Student SNNs on edge nodes via knowledge distillation. Edge nodes process real-time event streams and only offload low-confidence “hard examples” to the cloud, significantly reducing bandwidth usage.

Domain	Task	Approach / Model	Hardware	Key Performance Metrics	Ref.
CV	Neural Rendering	Spiking-NeRF (Hybrid SNN)	GPU/Simulated	Quality: Comparable PSNR; Energy: 2.27 $\times$ reduction vs. NeRF	[ 153 ]
	Gesture Recog.	OSBC (One-shot Pruning)	DVS128-Gesture	Sparsity: 97%; Acc Loss: 1.7%; Method: Post-training Quant.	[ 154 ]
Robotics	Visual Place Recog.	Modular SNN Ensembles	Resource Constrained	Compact modules (1.5k neurons); Sequence matching improves R@1	[ 155 ]
	Autonomous Agents	SNN4Agents (Quantization)	Event Sensors	Acc: 84.1%; Mem: $-$ 68.8%; Eff: 4.0 $\times$ gain	[ 117 ]
IoT	HAR (Multimodal)	SNN-driven fusion (Event + Skeleton); SNN-Mamba	N/A	High efficiency via sparse multimodal fusion	[ 156 ]
	Keyword Recog.	On-chip learning SNN	Commodity Neuro.	Latency: $<1$ ms	[ 157 ]

TABLE IV: Exemplary Applications of SNNs in Edge Computing (2022–2025)

Challenge Area	Specific Challenge	Current Research Approaches & Thrusts	Key Refs.
Training Complexity	Non-differentiable spike events	Surrogate Gradients (SG) ; Event-Driven Learning (STD-ED, MPD-ED); Differentiable Spike (Dspike)	[ 90 , 24 ]
	Gradient vanishing & “Dead neuron”	Learnable SGs ; Adaptive Gradient Rules; Threshold-dependent Batch Norm (tdBN); Activity regularization	[ 184 , 24 ]
	Bio-plausible scalability (STDP)	Hybrid learning (e.g., R-STDP); Supervised STDP variants; Combining STDP with backprop	[ 89 , 64 ]
Scalability	Performance on large datasets (e.g., ImageNet)	ANN-to-SNN Conversion ; SNN-specific deep architectures (Spiking Transformers); Hybrid models	[ 107 , 185 ]
Hardware Constraints	Memory Wall & Fan-in/out limits	Co-design Frameworks (e.g., QUEST); In-memory computing; SNN-specific pruning/quantization (OSBC)	[ 116 , 111 ]
Hardware Constraints	Inter-chip comm. & Heterogeneity	Optimized NoC designs; Standardized IR (e.g., NIR); Platform-agnostic frameworks (Lava)	[ 109 , 138 ]

TABLE V: Major Challenges in Deploying SNNs at the Edge and Current Research Thrusts

Fig. 7: Architectural Comparison. (a) Traditional Von Neumann architecture separates memory and processing. The data bus (shown as parallel lines) becomes a bottleneck. (b) Neuromorphic architecture integrates memory and computation (M+C) into distributed cores.

Fig. 8: Conceptual Quantum-Neuromorphic Synergy. Quantum algorithms (e.g., QAOA) are utilized to solve NP-hard optimization problems inherent in SNN design, such as Neural Architecture Search (NAS) or synaptic routing, enabling the deployment of highly optimized SNNs on neuromorphic hardware.

Neuromorphic Computing

Neuromorphic computing uses brain-inspired, event-driven algorithms and hardware to process information with low power and latency.

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L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma

Centre for Advanced Electronics, Indian Institute of Technology Indore, Simrol 453552, Indore, India · Dept. of Electrical Engineering, Indian Institute of Technology Indore, Simrol 453552, Indore, India

Efficient Neural Network Inference Spiking Neural Networks FPGA-Based Neural Network Acceleration Edge Inference

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Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.

Abstract

Neuromorphic Computing

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