cs.ARApr 4, 2026

L-SPINE: A Low-Precision SIMD Spiking Neural Compute Engine for Resource-efficient Edge Inference

Authors: Sonu Kumar, Mukul Lokhande, Santosh Kumar Vishvakarma

Organizations: Centre for Advanced Electronics, Indian Institute of Technology Indore, Simrol 453552, Indore, India · Dept. of Electrical Engineering, Indian Institute of Technology Indore, Simrol 453552, Indore, India

Read PDF
Ask AI
Cite

Copy citation

DOINot available for this paper

Abstract

Spiking Neural Networks (SNNs) offer a promising solution for energy-efficient edge intelligence; however, their hardware deployment is constrained by memory overhead, inefficient scaling operations, and limited parallelism. This work proposes L-SPINE, a low-precision SIMD-enabled spiking neural compute engine for efficient edge inference. The architecture features a unified multi-precision datapath supporting 2-bit, 4-bit, and 8-bit operations, leveraging a multiplier-less shift-add model for neuron dynamics and synaptic accumulation. Implemented on an AMD VC707 FPGA, the proposed neuron requires only 459 LUTs and 408 FFs, achieving a critical delay of 0.39 ns and 4.2 mW power. At the system level, L-SPINE achieves 46.37K LUTs, 30.4K FFs, 2.38 ms latency, and 0.54 W power. Compared to CPU and GPU platforms, it reduces inference latency from seconds to milliseconds, achieving an up to three orders-of-magnitude improvement in energy efficiency. Quantisation analysis shows that INT2/INT4 configurations significantly reduce memory footprint with minimal accuracy loss. These results establish L-SPINE as a scalable and efficient solution for real-time edge SNN deployment.

Figures & tables

Fig. 1: System-level architecture of the proposed L-SPINE accelerator integrating pico-rv32 RISC-V, spike encoding modules, and a 2D SIMD-enabled neuron processing array for efficient SNN inference.
Fig. 2: Detailed datapath for Proposed SIMD-enabled multi-precision compute engine supporting configurable 16x 2-bit, 4x 4-bit, and 1x 8-bit operations using a reconfigurable shift-add logic integrated in LIF neuron computation.
Fig. 3: Design and evaluation flow of the proposed L-SPINE architecture, including SNN training, quantization, hardware mapping, and FPGA-based validation.
Fig. 4: Comparison of accuracy and memory footprint with the state-of-the-art SNN quantisation, STBP [ 14 ] , ADMM [ 15 ] , Trunc [ 16 ] .
Fig. 5: Impact of precision scaling on SNN accuracy across INT2, INT4, INT8, and FP32 configurations.
DesignLUTsFFsDelay (ns)Power (mW)
TVLSI’26 [ 34 ]17708621.418.9
TCAS-II’24 [ 35 ]805417184.6222.5
MP-RPE [ 35 ]806510725.5621.8
Iterative CORDIC H&H [ 19 ]23444605.0011.6
PWL H&H [ 19 ]291302543039.0685.0
Parallel CORDIC H&H [ 19 ]860325022815.78140.0
TABLE I: Comparison for Neurons’ FPGA Resources utilization [ 42 , 28 , 29 , 31 , 27 ]
DesignLUTs (K)FFs (K)Latency (ms)Power (W)
TVLSI’26 [ 34 ]118.657.85.041.85
TRETS’23 [ 32 ]115.0115.021.462.10
TCAD’23 [ 23 ]170.4113.27.382.40
Iterative CORDIC H&H [ 19 ]157.030.820.501.95
Multiplier-less H&H [ 43 ]359.2190.031.544.20
RAM H&H [ 43 ]317.3104.035.603.85
TABLE II: Hardware resource comparison with SoTA accelerators (VC707 FPGA) [ 40 , 41 , 36 ]
More in this topic

Efficient Neural Network Inference

Efficient neural network inference reduces the time, memory, and energy needed to run trained models across hardware and deployment settings.

See all 465 papers

Explore similar work

CardsList

  1. SPARQ: Spiking Early-Exit Neural Networks for Energy-Efficient Edge AI

    Mar 15, 2026Parth Patne, Mahdi Taheri, Ali Mahani +3Spiking Neural NetworksEnergy-Efficient ML

    Brandenburg Technical University, Cottbus, Germany · Tallinn University of Technology, Tallinn, Estonia · Shahid Bahonar University of Kerman, Iran +2

  2. Spiker-LL: An Energy-Efficient FPGA Accelerator Enabling Adaptive Local Learning in Spiking Neural Networks

    May 18, 2026Alessio Caviglia, Filippo Marostica, Alessandro Savino +1On-Device TrainingEnergy-Efficient ML

    Control and Computer Engineering Department, Politecnico di Torino, Turin, Italy

  3. SNAP-V: A RISC-V SoC with Configurable Neuromorphic Acceleration for Small-Scale Spiking Neural Networks

    Mar 12, 2026Kanishka Gunawardana, Sanka Peeris, Kavishka Rambukwella +4Neuromorphic ComputingEfficient Neural Network Inference

    Department of Computer Engineering, Faculty of Engineering, University of Peradeniya, Peradeniya 20400, Sri Lanka