DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration

Shubham Kumar; Vijay Pratap Sharma; Vaibhav Neema; Santosh Kumar Vishvakarma

cs.ARApr 6, 2026

DHFP-PE: Dual-Precision Hybrid Floating Point Processing Element for AI Acceleration

Authors: Shubham Kumar, Vijay Pratap Sharma, Vaibhav Neema, Santosh Kumar Vishvakarma

Organizations: Institute of Engineering and Technology, Devi Ahilya University, Indore, India · NSDCS Research Group, Indian Institute of Technology Indore, India

Abstract

The rapid adoption of low-precision arithmetic in artificial intelligence and edge computing has created a strong demand for energy-efficient and flexible floating-point multiply-accumulate (MAC) units. This paper presents a dual-precision floating-point MAC processing element supporting FP8 (E4M3, E5M2) and FP4 (2 x E2M1, 2 x E1M2) formats, specifically optimized for low-power and high-throughput AI workloads. The proposed architecture employs a novel bit-partitioning technique that enables a single 4-bit unit multiplier to operate either as a standard 4 x 4 multiplier for FP8 or as two parallel 2 x 2 multipliers for 2-bit operands, achieving maximum hardware utilization without duplicating logic. Implemented in 28 nm technology, the proposed PE achieves an operating frequency of 1.94 GHz with an area of 0.00396 mm^2 and power consumption of 2.13 mW, resulting in up to 60.4% area reduction and 86.6% power savings compared to state-of-the-art designs, making it well suited for energy-constrained AI inference and mixed-precision computing applications when deployed within larger accelerator architectures.

Figures & tables

Fig. 1: Typical AI Accelerator architecture with emphasis on the Processing Element (PE).

Fig. 2: Accelerated GPU performance gains enabled by reduced-precision numerical formats. Source: AMD [ 19 ] .

Fig. 3: Proposed bit-partitioning method and Unit Multiplier: (a) 4-bit operand for FP8; (b) 2-bit operand for FP4

Fig. 4: Datapath of the proposed fully-pipelined dual-precision PE.

Fig. 5: Implementation of variable precision MAC. (a) Combination MAC.(b) Split MAC. (c) Bit-Split-and-combination MAC.

Fig. 6: Area and power variations subject to different clock period constraints: Typical corner ; Slow corner.

Fig. 7: Exponent Comparison Using EC+LUT for Mixed-Precision MAC.

Design	FPGA Platform	Freq. (MHz)	Power (mW)	LUT	FF	IO
TVLSI’25 [5]	VC707	263	0.35	405	116	–
TVLSI’22 [6]	VCU129	357	0.378	8065	1072	357
TCASII’24 [7]	VCU129	216.5	0.296	8054	1718	357
TCASI’25 [8]	ZCU102	173.2	0.061	1971	1096	–
This Work	VCU129	180	0.028	106	69	29

TABLE I: Comparison of FPGA Resource Utilization

Design	Node (nm)	Volt (V)	Freq (MHz)	Area (mm 2 )	Power (mW)	Precisions	Throughput			Energy Efficiency
							(GFLOPS)			(GFLOPS/W)
							FP16	FP8	FP4	FP16	FP8	FP4
TVLSI’21 [1]	22	0.8	923	0.049	8.6	FP64–FP8	12.67	25.33	–	1180	2950	–
GLSVLSI’23 [2]	28	0.8	2500	0.00987	48.4	FP4–FP8, FP12	20	20	–	413	413	–
ISCAS’24 [3]	28	1.0	160	1.84	67.4	FXP4/8, FP16, FP32	157	157	–	2329	2329	–
ASPDAC’25 [4]	28	0.9	200	0.0016	0.234	FP4–FP8, FP12	–	0.46	1.39	–	1948	5940

TABLE II: Comparison of Multi-Precision MAC/Accelerator Designs

Stage	Area ( $\mu$ m 2 )	Power (mW)	Delay (ns)
S0 (Input Decode)	582.12	0.314	0.076
S1 (Multiplication)	1137.31	0.613	0.148
S2 (Alignment Shifter)	370.26	0.200	0.048
S3 (Accumulation)	928.22	0.500	0.121
S4 (Normalization)	774.18	0.417	0.101
S5 (Output Encode)	166.72	0.0898	0.0216

TABLE III: Performance Summary of the Proposed PE Design

AI Accelerator Inference

AI accelerator inference studies hardware and software for running neural networks faster and more efficiently across data-center, edge, and mobile devices.

See all 102 papers

Precision-Aware Variable Bit Processing Elements for Hardware-Efficient Systolic Array Designs
Aug 23, 2026Dantu Nandini Devi, Madhav RaoApproximate Computing AI Accelerator Inference
Department of Electronics & Communication Engineering, IIIT-Bangalore, Karnataka, India
CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications
Feb 22, 2026Sonu Kumar, Mohd Faisal Khan, Mukul Lokhande +1AI Accelerator Inference Efficient Neural Network Inference
Centre for Advanced Electronics, IIT Indore. · NSDCS Research Group, Dept. of Electrical Engineering at IIT Indore.
The AetherFloat Family: Block-Scale-Free Quad-Radix Floating-Point Architectures for AI Accelerators
Feb 26, 2026Keita MorisakiStochastic Rounding AI Accelerator Inference
Independent Hardware/Software Co-Design Researcher Shinagawa City, Tokyo, Japan

Aug 23, 2026J/K move · Enter open · S save

Precision-Aware Variable Bit Processing Elements for Hardware-Efficient Systolic Array Designs

Dantu Nandini Devi, Madhav Rao

Department of Electronics & Communication Engineering, IIIT-Bangalore, Karnataka, India

Approximate Computing AI Accelerator Inference Efficient Neural Network Inference

Open paper AskPDF arXiv

Systolic arrays (SAs) have emerged as prominent hardware accelerators for matrix operations in deep learning, while floating point number formats enable precision control across computational domains. This research investigates approximate computing techniques for floating point (FP) multipliers in Weight Stationary Systolic Arrays, focusing on IEEE 754 (FP32), TensorFloat-32 (TF32), and Brain Floating point (BF16) formats. By integrating partial product matrix (PPM) column truncation with positive and negative compressors in the FP multiplier architecture, we optimize the trade-off between computational efficiency and accuracy. NSGA-II optimization algorithm was employed to explore the vast design space for evolving FP multiplier designs, towards achieving substantial hardware improvements while maintaining acceptable output quality. Substantial hardware benefits were observed in the FP multiplier designs across various applications, while preserving output quality. The FP approximated Processing Elements designed in the SA was found to offer comparable CNN accuracy for models trained on MNIST, F-MNIST, and CIFAR-10 dataset. The FP approximated SA designs that fall in the top 10 CNN performance offered substantial hardware gains in the range of 66% to 92% footprint savings, 60% to 93% of power benefits with 21% to 54% improvement in the delay when compared with the corresponding exact implementations mentioned in the literature for running the model trained on CIFAR-10 dataset. The TF32 and BF16 approximated SA designs also achieved substantial gains while maintaining comparable CNN accuracy. Our findings confirm that targeted approximation in FP multiplier design significantly improves the efficiency of hardware accelerators for error-tolerant applications, establishing an effective approach to hardware resource optimization in contemporary computing architectures.

Abstract

AI Accelerator Inference

Explore similar work

Precision-Aware Variable Bit Processing Elements for Hardware-Efficient Systolic Array Designs

CORVET: A CORDIC-Powered, Resource-Frugal Mixed-Precision Vector Processing Engine for High-Throughput AIoT applications

The AetherFloat Family: Block-Scale-Free Quad-Radix Floating-Point Architectures for AI Accelerators