R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII

Zewei Zhou; Jiajun Zou; Jiajia Zhang; Ao Yang; Ruichao He; Haozheng Zhou; Ao Liu; Jiawei Liu

cs.CVApr 9, 2026

R2G: A Multi-View Circuit Graph Benchmark Suite from RTL to GDSII

Authors: Zewei Zhou, Jiajun Zou, Jiajia Zhang, Ao Yang, Ruichao He, Haozheng Zhou, Ao Liu, Jiawei Liu, +3 more

Organizations: Nanjing University of Science and Technology · The Chinese University of Hong Kong

Abstract

Graph neural networks (GNNs) are increasingly applied to physical design tasks such as congestion prediction and wirelength estimation, yet progress is hindered by inconsistent circuit representations and the absence of controlled evaluation protocols. We present R2G (RTL-to-GDSII), a multi-view circuit-graph benchmark suite that standardizes five stage-aware views with information parity (every view encodes the same attribute set, differing only in where features attach) over 30 open-source IP cores (up to $10^6$ nodes/edges). R2G provides an end-to-end DEF-to-graph pipeline spanning synthesis, placement, and routing stages, together with loaders, unified splits, domain metrics, and reproducible baselines. By decoupling representation choice from model choice, R2G isolates a confound that prior EDA and graph-ML benchmarks leave uncontrolled. In systematic studies with GINE, GAT, and ResGatedGCN, we find: (i) view choice dominates model choice, with Test R $^2$ varying by more than 0.3 across representations for a fixed GNN; (ii) node-centric views generalize best across both placement and routing; and (iii) decoder-head depth (3--4 layers) is the primary accuracy driver, turning divergent training into near-perfect predictions (R $^2$$>$ 0.99). Code and datasets are available at https://github.com/ShenShan123/R2G.

Figures & tables

Figure 1: Benchmark and dataset evolution across graph ML and EDA, highlighting R 2 G’s unique position at their intersection as a stage-aware, multi-view circuit-graph benchmark suite.

Designs	Category	Circuit & Graph Statistics					Function
Designs		#Gates	#Nets	#IOs	#Nodes	#Edges
ss_pcm	Audio controller	463	521	28	2.44k	2.88k	pulse code modulation
ac97_ctrl	Audio controller	10509	12531	132	58.22k	70.60k	AC97 Audio Codec Controller
vga_lcd	Video controller	97688	110587	198	531.33k	650.84k	VGA/LCD Display Controller
des3_area	Crypto core	1529	1655	190	9.78k	12.46k	3DES Enc/Dec Module
systemcdes	Crypto core	2663	2788	197	14.17k	17.02k	SystemC DES Encryption/Decryption Core

Table 1: Design corpus statistics including circuit sizes and corresponding graph scale (#Nodes and #Edges under view (b)) for representative open-source IP cores.

Figure 2: OpenROAD RTL-to-GDSII post-end flow including floorplanning, placement (global and detailed), clock-tree synthesis, routing (global and detailed), and signoff. R2G focuses on placement and routing, while earlier stages provide constraints and contextual information.

Figure 3: Original circuit schematic (a) and five complementary circuit graph views (b–f) used in R2G: (b) all-elements-as-nodes, (c) pins-as-edges, (d) nets-as-edges, (e) net–gate incidence edges, (f) net edges without pin nodes. These views support placement and routing analyses under different supervision granularities.

Unit	Name	Type	Definition	Notes
Gate	x	feat. (rout.)	Gate x (DBU)	Node (b/c/d/f); edge (e)
Gate	y	feat. (rout.)	Gate y (DBU)	Node (b/c/d/f); edge (e)
Gate	cell_type	feat.	Integer encoding of gate type	Node (b/c/d/f); edge (e)
Gate	orientation	feat.	Orientation code (0–7)	Node (b/c/d/f); edge (e)
Gate	area	feat.	Gate area (tech lib)	Node (b/c/d/f); edge (e)
Gate	place_flag	feat.	Placement status	Node (b/c/d/f); edge (e)

Table 2: Definitions of features/labels for circuit components in terms of views.

		(b)			(c)			(d)			(e)			(f)
Split	Model	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$
Train	GINE	0.2859	0.6117	0.9554	0.5061	0.8678	0.9017	0.3272	0.4516	0.7984	0.1649	0.2936	0.9137	0.3334	0.4563	0.7941
	ResGatedGCN	0.3097	0.655	0.9489	0.4808	0.798	0.9169	0.3263	0.4477	0.8016	0.1819	0.3508	0.8767	0.3339	0.4609	0.7938
	GAT	0.4762	1.1623	0.839	1.0883	1.8336	0.5611	0.4834	0.6394	0.5958	0.1812	0.3374	0.8861	0.6848	0.8683	0.2541
Validation	GINE	0.6332	1.2972	0.8219	1.095	1.6276	0.6929	0.3604	0.4516	0.748	0.4134	0.7032	0.5137	0.5431	0.6576	0.4674
	ResGatedGCN	0.7485	1.4158	0.7879	0.8544	1.2884	0.8075	0.3772	0.4809	0.7142	0.3637	0.5815	0.6675	0.4462	0.5689	0.6108

Table 3: Placement results across views (b–f) and splits. Lower MAE/RMSE is better; higher R 2 is better.

		(b)			(c)			(d)			(e)			(f)
Split	Model	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$
Train	GINE	0.2520	0.7796	0.9257	0.7011	1.3372	0.8716	0.4019	0.5419	0.7105	0.4188	0.5744	0.6746	0.1477	0.2130	0.9551
	ResGatedGCN	0.3041	0.6848	0.9427	0.5291	0.9252	0.9385	0.3947	0.5400	0.7126	0.3805	0.5217	0.7318	0.5545	0.7204	0.4886
	GAT	0.3944	1.0904	0.8547	1.4430	2.5930	0.5170	0.5659	0.7216	0.4871	0.2914	0.4246	0.8224	0.8544	1.0354	-0.0618
Validation	GINE	0.8523	1.7891	0.6529	1.7403	2.8566	0.4877	0.3892	0.5013	0.6601	0.3839	0.5155	0.6370	0.2670	0.4098	0.8143
	ResGatedGCN	0.7971	1.5267	0.7472	1.0107	1.7078	0.8169	0.4222	0.5288	0.6218	0.3929	0.5237	0.6255	0.6243	0.7871	0.1746

Table 4: Routing results across views (b–f) and splits. Lower MAE/RMSE is better; higher R 2 is better.

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R² $\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R² $\uparrow$	#Param.
3	0.3489	1.0454	0.8851	0.78 M	0.3319	1.0296	0.8885	0.98 M
4	0.2594	1.0158	0.8915	0.98 M	0.3249	1.0617	0.8815	1.24 M
5	0.2991	1.0445	0.8853	1.18 M	0.2923	1.0699	0.8797	1.51 M
6	0.3312	1.2536	0.8348	1.38 M	0.3327	1.0833	0.8766	1.77 M

Table 5: Placement on view (b) vs. GNN depth (3–6). Compact stacks (3–4) yield highest accuracy; deeper (6) underperform.

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R² $\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R² $\uparrow$	#Param.
3	0.3220	1.0691	0.8759	0.78 M	0.3439	1.0682	0.8762	0.98 M
4	0.3466	1.1503	0.8664	0.98 M	0.2977	1.1141	0.8653	1.24 M
5	0.2845	1.0969	0.8694	1.18 M	0.3188	1.0768	0.8742	1.51 M
6	0.3670	1.0910	0.8708	1.38 M	0.3892	1.1495	0.8566	1.77 M

Table 6: Routing on view (b) vs. GNN depth (3–6). Performance peaks at 3 layers for both architectures; deeper stacks show diminishing returns.

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	#Param.
1	0.4708	1.1886	0.8514	0.91 M	3.1580	3.3342	-0.1689	1.18 M
2	0.3414	1.1184	0.8685	0.98 M	0.3249	1.0542	0.8832	1.24 M
3	0.0870	0.3329	0.9883	1.05 M	0.0963	0.3251	0.9889	1.31 M
4	0.0703	0.1909	0.9962	1.11 M	0.1421	0.3223	0.9891	1.38 M

Table 7: Placement on view (b) vs. head layers (1–4). Increasing head capacity stabilizes training and drives accuracy; 3–4 head layers deliver near-perfect R 2 across architectures.

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R 2 $\uparrow$	#Param.
1	13.9757	54.1022	nan	0.91 M	nan	nan	nan	1.18 M
2	0.3425	1.1414	0.8586	0.98 M	0.2892	1.1276	0.8620	1.24 M
3	0.0761	0.3173	0.9891	1.05 M	0.1230	0.3823	0.9841	1.31 M
4	0.0542	0.1802	0.9965	1.11 M	0.2482	0.3824	0.9841	1.38 M

Table 8: Routing on view (b) vs. head layers (1–4). Shallow heads are unstable; accuracy improves sharply at 3 and is near-perfect at 4. Prefer 3–4 head layers for robust routing.

Appendix figures & tables8 assets

Supplementary material from the paper’s appendix.

Appendix

Benchmark Suite		Category	Level	Task	Statistics			Metric
Benchmark Suite		Category	Level	Task	#Node/G	#Edge/G	#Degree/G	Metric
OGB	ogbn-products	Product	node	C	2,449,029	61,859,140	50.5	Accuracy
	ogbn-mag	Academic	node	C	1,939,743	21,111,007	21.77	Accuracy
	ogbl-ppa	Bio	edge	L	576,289	30,326,273	105.2	Hits@100
	ogbl-citation2	Citation	edge	L	2,927,963	30,561,187	20.9	MRR
TU	QM9	Molecules	node	R	18	19	2.07	MAE

Appendix

Table 9: Overview of existing graph datasets. Tasks include Classification (C), Regression (R), and Link prediction (L).

#nodes

#edges

avg_degree

avg_shortest path

Cat.

RTL2G

(b)

(c)

(d)

(e)

(f)

(b)

(c)

(d)

(e)

(f)

(b)

(c)

(d)

(e)

(f)

(b)

(c)

(d)

(e)

(f)

A/V ctrl.

ss_pcm

2.44k

1.01k

1.89k

1.46k

0.46k

2.88k

2.02k

2.36k

1.66k

1.01k

2.37

4.01

2.49

2.28

4.35

12.07

3.00

9.81

12.69

4.05

ac97_ctrl

58.22k

22.99k

40.86k

30.63k

10.36k

70.60k

47.20k

52.19k

36.83k

23.50k

2.43

4.11

2.55

2.40

4.54

13.41

3.00

13.76

21.20

5.65

vga_lcd

531.33k

206.01k

369.72k

275.41k

94.51k

650.84k

445.88k

455.43k

325.55k

197.12k

2.45

4.33

2.46

2.36

4.17

14.33

3.02

24.37

31.42

8.00

Average

197.33k

76.67k

137.49k

102.50k

35.11k

241.44k

165.03k

170.00k

121.35k

74.08k

2.42

4.15

2.50

2.35

4.35

13.27

3.01

15.98

21.77

5.90

Crypto Core

des3_area

9.78k

3.65k

7.94k

6.33k

1.80k

12.46k

9.29k

11.17k

9.41k

5.10k

2.55

5.09

2.81

2.97

5.66

18.16

3.28

15.43

12.42

6.13

Appendix

Table 10: Comparison of graph statistics across graph views and design categories.

Hyper	lr	wd	hid_dim	act	gnn_layer	dropout	head_layer	head_dim
(b)
GINE	1e-4	1e-4	256	relu	4	0.3	2	256
ResGatedGCN	1e-4	1e-4	256	relu	4	0.3	2	256
GAT	1e-4	1e-4	256	relu	4	0.3	2	256
(c)
GINE	1e-4	1e-4	256	relu	4	0.3	2	256

Appendix

Table 11: Placement Task Hyperparameters for Different Graph Views

Hyper	lr	wd	hid_dim	act	gnn_layer	dropout	head_layer	head_dim
(b)
GINE	1e-4	1e-4	256	leakyrelu	4	0.3	2	256
ResGatedGCN	1e-4	1e-4	256	leakyrelu	4	0.3	2	256
GAT	1e-4	1e-4	256	leakyrelu	4	0.3	2	256
(c)
GINE	1e-4	1e-4	256	leakyrelu	4	0.3	2	256

Appendix

Table 12: Routing Task Hyperparameters for Different Graph Views

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.
3	0.4552	0.6098	0.6811	0.83M	0.4521	0.6026	0.6886	1.62M
4	0.4451	0.5937	0.6975	1.03M	0.4670	0.6197	0.6704	2.08M
5	0.4837	0.6467	0.6414	1.23M	0.4700	0.6077	0.6833	2.54M
6	0.4063	0.5478	0.7427	1.42M	0.5449	0.6786	0.6051	3.00M

Appendix

Table 13: Placement on view (d) vs. GNN depth (3–6).

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.
3	0.5470	0.7172	0.6000	0.83M	0.5732	0.7557	0.5558	1.62M
4	0.6111	0.7920	0.5122	1.03M	0.6007	0.7826	0.5237	2.08M
5	0.5062	0.6805	0.6398	1.22M	0.5413	0.7091	0.6090	2.54M
6	0.5964	0.7571	0.5542	1.42M	0.6803	0.8942	0.3782	3.00M

Appendix

Table 14: Routing on view (d) vs. GNN depth (3–6).

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.
1	nan	nan	nan	0.90M	nan	nan	nan	1.95M
2	0.4451	0.5937	0.6975	1.03M	0.4670	0.6197	0.6704	2.08M
3	0.4337	0.5804	0.7109	1.10M	0.4576	0.6043	0.6866	2.15M
4	0.4359	0.5851	0.7062	1.16M	0.4418	0.5922	0.6990	2.21M

Appendix

Table 15: Placement on view (d) vs. head layers (1–4).

	GINE				ResGatedGCN
#layers	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.	MAE $\downarrow$	RMSE $\downarrow$	R ${}^{2}\uparrow$	#Param.
1	nan	nan	nan	0.90M	nan	nan	nan	1.95M
2	0.6111	0.792	0.5122	1.03M	0.6007	0.7826	0.5237	2.08M
3	0.4637	0.6148	0.7060	1.09M	0.5678	0.7551	0.5565	2.14M
4	0.4971	0.6636	0.6581	1.16M	0.5445	0.7099	0.6089	2.21M

Appendix

Table 16: Routing on view (d) vs. head layers (1–4).

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Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation

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Graph Neural Networks Graph Representation Learning Electronic Design Automation

Open paper AskPDF arXiv

EDA problems are graph-structured, but not all graph-structured problems call for the same GNN computation. We argue that successful GNN-for-EDA methods are those whose propagation, aggregation, and supervision align with the native algebra of the target task. Concretely: static timing analysis is a max-plus/min-plus recurrence on a topologically ordered DAG, structurally aligned with asynchronous DAG-GNNs; placement is governed by hypergraph wirelength and density penalties and is exploited by differentiable placers rather than by message-passing GNNs alone; routing congestion is a sparse demand-supply field over a layout grid; switching-activity propagation is a probabilistic recurrence on a directed netlist; IR drop is a linear system on the power-delivery network; and analog symmetry extraction is a discrete constraint-prediction problem on schematic graphs. Through these task-by-task alignments we (i) review the GNN architectural toolkit relevant to circuits, (ii) formalize how circuit graphs differ from generic graphs (directed, heterogeneous, multi-scale, with sequential and clock structure), (iii) characterize where current methods succeed and where the algebra-architecture mismatch limits them, and (iv) identify failure modes--stage leakage, proxy-to-signoff gap, calibration, and design-distribution shift--that we believe are likely to dominate the next phase of work. We position the paper as a GNN-for-EDA, task-aligned analysis rather than a comprehensive AI-for-chip-design survey. Continuous SE(3)-equivariant geometric GNNs are usually mismatched to Manhattan digital layout, and LLM-for-RTL, HLS, and RL/diffusion-based topology generation are outside our scope.

Abstract

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