IR drop analysis is essential in physical chip design to ensure the power integrity of on-chip power delivery networks. Traditional Electronic Design Automation (EDA) tools have become slow and expensive as transistor density scales. Recent works have introduced machine learning (ML)-based methods that formulate IR drop analysis as an image prediction problem. These existing ML approaches fail to capture both local and long-range dependencies and ignore crucial geometrical and topological information from physical layouts and logical connectivity. To address these limitations, we propose GIF, a Generative IR drop Framework that uses both geometrical and topological information to generate IR drop images. GIF fuses image and graph features to guide a conditional diffusion process, producing high-quality IR drop images. For instance, On the CircuitNet-N28 dataset, GIF achieves 0.78 SSIM, 0.95 Pearson correlation, 21.77 PSNR, and 0.026 NMAE, outperforming prior methods. These results demonstrate that our framework, using diffusion based multimodal conditioning, reliably generates high quality IR drop images. This shows that IR drop analysis can effectively leverage recent advances in generative modeling when geometric layout features and logical circuit topology are jointly modeled. By combining geometry aware spatial features with logical graph representations, GIF enables IR drop analysis to benefit from recent advances in generative modeling for structured image generation.
Figures & tables
Method
Layout Power Maps
Geometry-aware Layout Features
Logical Topology
Generative Modeling
PowerNet [ 27 ]
✓
✗
✗
✗
MAVIREC [ 4 ]
✓
✗
✗
✗
PDNNet [ 29 ]
✓
✗
✓
✗
Ours (GIF)
✓
✓
✓
✓
Table 1: Comparison of IR-drop learning approaches.
Figure 1: Overview of the proposed framework. (a) Geometric features creation from DEF/LEF files and power reports, (b) Topological features creation, and (c) A diffusion-based UNet predicts the noise ϵ , conditioned on features via AdaGN+FiLM and on graph tokens via gated cross-attention, (d) Generated IR drop map.
Figure 2: Visualization of additional features and ground-truth IR-drop map for the RISCY design from the N14 technology dataset. From left to right: (a) Cell Density , (b) RUDY Short , (c) Global Routing Vertical Overflow , and (d) IR-drop Ground Truth .
Feature Group
Channels
Ieff
Reff
Cell density
Cden(x,y)
✓
✗
Macro region
M(x,y)
✓
✗
RUDY-based demand
RUDY,RUDYpin
✓
✗
RUDY-based demand
RUDYlong,RUDYshort
✓
✗
Routing overflow
OHeGR,OVeGR
✗
✓
Routing overflow
OHGR,OVGR
✗
✓
Table 2: Layout-aware feature groups fused with power maps and their contribution to the current proxy Ieff and the resistance proxy Reff .
Figure 3: Graph construction: (a) Gate level netlist and graph construction attributes, (b) Instance (GCell) placement information, each instance is placed on grid (cx,cy) , annotated with its bounding - box coordinates (l,b,r,t) , and pin count p , (c) Constructed graph representation with node feature vector xv=[cx,cy,l,b,r,t,p] .
Table 6
Conditioning
ControlNet
PSNR ↑
SSIM ↑
MAE ↓
RMSE ↓
Pearson ↑
Spearman ↑
24-ch images
✗
19.218
0.699
0.0378
0.1103
0.9069
0.4949
34-ch images
✗
19.542
0.739
0.0352
0.1063
0.9118
0.4973
24-ch images
✓
19.255
0.711
0.0374
0.1098
0.9065
0.4865
34-ch images
✓
19.583
0.766
0.0345
0.1058
0.9127
0.5033
34-ch + graph (K=32, topk)
✗
19.519
0.611
0.0383
0.1066
0.9130
0.5107
34-ch + graph (K=32, topk)
✓
19.307
0.762
0.0363
0.1091
0.9064
0.4976
Table 5: Quantitative generation results on the CircuitNet-N28 [ 13 , 2 ] dataset.
Method
NMAE ↓
PSNR ↑
SSIM ↑
Pear ↑
PowerNet [ 27 ]
0.149
11.60
0.56
0.77
MAVIREC [ 4 ]
0.039
18.27
0.68
0.91
PDNNet [ 29 ]
0.028
19.35
0.72
0.92
Ours (GIF)
0.026
21.77
0.78
0.95
Table 6: Comparison with SOTA methods on CircuitNet-N28
Figure A.1 : Modern chip design flow including physical design (orange) and IR-drop analysis (black).
Figure B.2 : ResBlock with FiLM conditioning. Timestep embedding and geometric layout features Xℓ produce affine scale shift pairs applied sequentially after each GroupNorm.
Figure B.3 : Cross-attention injection at the bottleneck. Topology tokens T serve as keys and values while spatial features serve as queries. The gate tanh(αℓ) , initialized to zero, controls the contribution of the topology signal.
Figure D.4 : SSIM and Spearman correlation across incremental model configurations on CircuitNet-N28. Left : SSIM improves as each component is added, reflecting improved spatial structure of the generated IR-drop map. Right : Spearman correlation across the same steps, showing improved hotspot severity ordering with each added component.
Design Family
Valid Graphs
Total Placements
RISCY
3373
3456
RISCY-FPU
3456
3456
Vortex-large
62
74
Vortex-small
0
96
nvdia-large
54
68
nvdia-small
88
93
Appendix
Table E.1 : Number of valid graphs constructed for CircuitNet-N14 (from the official metadata). Designs with all-zero placements produce no usable graphs.
Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50× faster sampling efficiency, and zero overlaps.
Peng Xie, Ke Xue, Yunqi Shi +6
1State Key Laboratory of Novel Software Technology, Nanjing University, China · School of Artificial Intelligence, Nanjing University, China · 3Huawei Noah’s Ark Lab, China
Utilities increasingly rely on planning and operational tools to cope with the increased penetrations of distributed energy resources, yet the lack of realistic, openly available datasets remains a major barrier for benchmarking and comparison. Traditional test feeders, and recently proposed large-scale synthetic networks alleviate this issue but are typically based on heuristic rules and do not learn directly from data. This paper proposes a generative framework based on Generative Adversarial Networks (GANs) to create power distribution network layouts using image-based representations. The model is trained on rasterised views of distribution systems and can operate in two modes: an unconditional configuration that learns layout patterns from the training dataset, and conditional configurations that incorporate geographical context such as street maps and the spatial distribution of consumers. The methodology includes dataset preparation from Geographic Information System (GIS) sources, GAN architecture design, and the analysis of training stability and image resolution. Results from three representative cases show that the proposed approach can reproduce the topologies of low (LV), medium (MV) and high voltage (HV) feeders and align generated layouts with underlying geographical structures. At the same time, the study reveals limitations related to training stability, resolution-dependent artefacts and limits, and the absence of explicit electrical constraints. The proposed framework constitutes a data-driven complement to existing synthetic network generation methods, and could be applied to propose distribution network layouts for the electrification of new areas. This would require future extensions towards power flow, electrically validated models.
Juan Manuel Garcia-Perez, Carlos Mateo
School of Engineering (ICAI), Comillas Pontifical University, Spain · Institute for Research in Technology (IIT), School of Engineering (ICAI), Comillas Pontifical University, Spain
The integration of artificial intelligence into computer-aided design frameworks has sparked a shift in the design of analog integrated circuits (ICs), transitioning the field from using manual and algorithmic-based solutions to adopting automated and intelligent paradigms. In this scenario, the GDSII file represents the industry-standard database containing the ultimate and most accurate source of information of the analog circuit, encapsulating the complex physical geometries and parasitic realities that define tape out performance. This paper proposes THEIA, a novel dataset containing thousands of layout images paired with question-answer conversations, along with a benchmark that employs a fine-tuned vision-language model (VLM) to analyze GDSII files of analog circuits, enabling designers to interact with and query physical layouts as intuitive, meaningful entities. Experimental results using thousands of analog designs across five realistic tasks demonstrate that the proposed fine-tuned VLM outperforms state-of-the-art general-purpose VLMs by a significant margin (up to 73%), highlighting a fundamental gap between general-purpose multimodal reasoning and domain-specific layout understanding.
Giuseppe Chiari, Michele Piccoli, Federico Viola +1