GIF: A Conditional Multimodal Generative Framework for IR Drop Imaging in Chip Layouts

Kiran Thorat; Nicole Meng; Mostafa Karami; Caiwen Ding; Yingjie Lao; Zhijie Jerry Shi

cs.CVApr 11, 2026

GIF: A Conditional Multimodal Generative Framework for IR Drop Imaging in Chip Layouts

Authors: Kiran Thorat, Nicole Meng, Mostafa Karami, Caiwen Ding, Yingjie Lao, Zhijie Jerry Shi

Organizations: University of Connecticut, USA · Tufts University, USA · University of Minnesota Twin Cities, USA

Abstract

IR drop analysis is essential in physical chip design to ensure the power integrity of on-chip power delivery networks. Traditional Electronic Design Automation (EDA) tools have become slow and expensive as transistor density scales. Recent works have introduced machine learning (ML)-based methods that formulate IR drop analysis as an image prediction problem. These existing ML approaches fail to capture both local and long-range dependencies and ignore crucial geometrical and topological information from physical layouts and logical connectivity. To address these limitations, we propose GIF, a Generative IR drop Framework that uses both geometrical and topological information to generate IR drop images. GIF fuses image and graph features to guide a conditional diffusion process, producing high-quality IR drop images. For instance, On the CircuitNet-N28 dataset, GIF achieves 0.78 SSIM, 0.95 Pearson correlation, 21.77 PSNR, and 0.026 NMAE, outperforming prior methods. These results demonstrate that our framework, using diffusion based multimodal conditioning, reliably generates high quality IR drop images. This shows that IR drop analysis can effectively leverage recent advances in generative modeling when geometric layout features and logical circuit topology are jointly modeled. By combining geometry aware spatial features with logical graph representations, GIF enables IR drop analysis to benefit from recent advances in generative modeling for structured image generation.

Figures & tables

Method	Layout Power Maps	Geometry-aware Layout Features	Logical Topology	Generative Modeling
PowerNet [ 27 ]	✓	✗	✗	✗
MAVIREC [ 4 ]	✓	✗	✗	✗
PDNNet [ 29 ]	✓	✗	✓	✗
Ours (GIF)	✓	✓	✓	✓

Table 1: Comparison of IR-drop learning approaches.

Figure 1: Overview of the proposed framework. (a) Geometric features creation from DEF/LEF files and power reports, (b) Topological features creation, and (c) A diffusion-based UNet predicts the noise $\epsilon$ , conditioned on features via AdaGN+FiLM and on graph tokens via gated cross-attention, (d) Generated IR drop map.

Figure 2: Visualization of additional features and ground-truth IR-drop map for the RISCY design from the N14 technology dataset. From left to right: (a) Cell Density , (b) RUDY Short , (c) Global Routing Vertical Overflow , and (d) IR-drop Ground Truth .

Feature Group	Channels	$I_{\mathrm{eff}}$	$R_{\mathrm{eff}}$
Cell density	$\text{C}_{\text{den}}(x,y)$	✓	✗
Macro region	$\text{M}(x,y)$	✓	✗
RUDY-based demand	$\text{RUDY},\;\text{RUDY}_{\text{pin}}$	✓	✗
RUDY-based demand	$\text{RUDY}_{\text{long}},\;\text{RUDY}_{\text{short}}$	✓	✗
Routing overflow	$\text{O}^{\mathrm{eGR}}_{H},\;\text{O}^{\mathrm{eGR}}_{V}$	✗	✓
Routing overflow	$\text{O}^{\mathrm{GR}}_{H},\;\text{O}^{\mathrm{GR}}_{V}$	✗	✓

Table 2: Layout-aware feature groups fused with power maps and their contribution to the current proxy

I_{\mathrm{eff}}

and the resistance proxy

R_{\mathrm{eff}}

Figure 3: Graph construction: (a) Gate level netlist and graph construction attributes, (b) Instance (GCell) placement information, each instance is placed on grid

(c_{x},c_{y})

, annotated with its bounding - box coordinates

(l,b,r,t)

, and pin count

p

, (c) Constructed graph representation with node feature vector

\mathbf{x}_{v}=[c_{x},\,c_{y},\,l,\,b,\,r,\,t,\,p]

Table 6

Conditioning	ControlNet	PSNR ↑	SSIM ↑	MAE ↓	RMSE ↓	Pearson ↑	Spearman ↑
24-ch images	✗	19.218	0.699	0.0378	0.1103	0.9069	0.4949
34-ch images	✗	19.542	0.739	0.0352	0.1063	0.9118	0.4973
24-ch images	✓	19.255	0.711	0.0374	0.1098	0.9065	0.4865
34-ch images	✓	19.583	0.766	0.0345	0.1058	0.9127	0.5033
34-ch + graph (K=32, topk)	✗	19.519	0.611	0.0383	0.1066	0.9130	0.5107
34-ch + graph (K=32, topk)	✓	19.307	0.762	0.0363	0.1091	0.9064	0.4976

Table 5: Quantitative generation results on the CircuitNet-N28 [ 13 , 2 ] dataset.

Method	NMAE $\downarrow$	PSNR $\uparrow$	SSIM $\uparrow$	Pear $\uparrow$
PowerNet [ 27 ]	0.149	11.60	0.56	0.77
MAVIREC [ 4 ]	0.039	18.27	0.68	0.91
PDNNet [ 29 ]	0.028	19.35	0.72	0.92
Ours (GIF)	0.026	21.77	0.78	0.95

Table 6: Comparison with SOTA methods on CircuitNet-N28

Figure 4: Qualitative IR-drop generation on CircuitNet-N28: (a) noise $x_{T}$ , (b) conditioning features (3-channels shown), (c) generated IR-drop $\hat{x}_{0}$ , (d) ground truth.

Model	PSNR ↑	SSIM ↑	MAE ↓	RMSE ↓	Pearson ↑	Spearman ↑
34-ch + ControlNet (no CFG)	14.156	0.513	0.0795	0.1996	0.8903	0.8133
34-ch + ControlNet (cfg-drop 0.1, no CFG at test)	14.987	0.558	0.0667	0.1797	0.9106	0.8284
34-ch + Graph (K=32, top-k) + ControlNet (no CFG)	14.143	0.4947	0.0797	0.1995	0.8892	0.8103
34-ch + Graph (K=32, top-k) + ControlNet (finetuned, no CFG)	14.455	0.5025	0.0758	0.1918	0.8974	0.8149

Table 7: Quantitative results on the CircuitNet-N14 dataset.

Figure 5: Qualitative IR-drop generation on CircuitNet-N14: (a) noise $x_{T}$ , (b) conditioning features (3-channels shown), (c) generated IR-drop $\hat{x}_{0}$ , (d) ground truth.

Appendix figures & tables5 assets

Supplementary material from the paper’s appendix.

Appendix

Figure A.1 : Modern chip design flow including physical design (orange) and IR-drop analysis (black).

Figure B.2 : ResBlock with FiLM conditioning. Timestep embedding and geometric layout features $X_{\ell}$ produce affine scale shift pairs applied sequentially after each GroupNorm.

Figure B.3 : Cross-attention injection at the bottleneck. Topology tokens

T

serve as keys and values while spatial features serve as queries. The gate

\tanh(\alpha_{\ell})

, initialized to zero, controls the contribution of the topology signal.

Figure D.4 : SSIM and Spearman correlation across incremental model configurations on CircuitNet-N28. Left : SSIM improves as each component is added, reflecting improved spatial structure of the generated IR-drop map. Right : Spearman correlation across the same steps, showing improved hotspot severity ordering with each added component.

Design Family	Valid Graphs	Total Placements
RISCY	3373	3456
RISCY-FPU	3456	3456
Vortex-large	62	74
Vortex-small	0	96
nvdia-large	54	68
nvdia-small	88	93

Appendix

Table E.1 : Number of valid graphs constructed for CircuitNet-N14 (from the official metadata). Designs with all-zero placements produce no usable graphs.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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Chip placement plays an important role in physical design. While generative models like diffusion models offer promising learning-based solutions, current methods have the following limitations: they use random synthetic data for pre-training, require long sampling times, and often result in overlaps due to their dependence on gradient-based solvers during the sampling process. To overcome these issues, we propose FlowPlace, which features mask-guided synthetic data generation, flow-based efficient training with flexible prior injection, and hard constraint sampling for overlap-free layouts. Experiments on OpenROAD and ICCAD 2015 benchmarks show FlowPlace achieves better PPA metrics, 10-50

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Abstract

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