Hardware-aware Low-latency Quantum Compilation with Data-driven Lightweight Error Detection for Early Fault-Tolerant Systems
Authors: Sumit Chongder
Organizations: Indian Institute of Technology Jodhpur · Inter-Disciplinary Research Platform, Quantum Information and Computation, Indian Institute of Technology Jodhpur, Jodhpur, Rajasthan 342037, India
Abstract
Noisy intermediate-scale quantum (NISQ) processors are entering an early fault-tolerance regime where full quantum error correction carries prohibitive resource costs, yet lightweight error detection can meaningfully improve algorithmic success rates. Existing compilation and error-detection toolchains treat these concerns in isolation, with no principled way to balance detection overhead against success probability under latency constraints. We present an integrated hardware-aware compilation and data-driven quantum error-detection (QED) framework that jointly optimises qubit mapping, SWAP insertion, and syndrome-schedule placement via a noise-weighted cost function and a learned multi-objective scheduler. Simulation experiments on an HPC cluster using GPU-accelerated density-matrix simulation (NVIDIA cuQuantum SDK) across VQE, phase-estimation, and Grover benchmarks, three noise profiles, and circuit sizes of 6-20 qubits (depths 10-160), show that joint co-design raises algorithmic success probability by up to 68 percent (95 percent CI: 60 percent to 76 percent) over SABRE on an 8-qubit VQE instance with post-selection.
High Performance Computing-Quantum Computing (HPCQC) platforms expose multiple Quantum Processing Units (QPUs) that may differ in size, topology, native gates, and noise characteristics. For current noisy devices, errors compound along the compiled circuits quickly, and minimizing them, that is, maximizing the circuits' execution fidelity, is essential for reliable results. Fidelity depends on the compilation to a specific target device: the same high-level circuit may produce different executables and, therefore, different expected fidelities across QPUs. We present a low-overhead fidelity-aware scheduling framework for multi-QPU systems based on a Graph Neural Network (GNN) that estimates, before compilation, the expected fidelity of each circuit on each available QPU. Then, a tunable scheduler uses these estimates to control the trade-off between execution fidelity and parallelism. Results show that this framework allows for approximating an exhaustive fidelity-based assignment, saving computational resources compared to a brute-force approach that compiles each circuit on every device.
Innocenzo Fulginiti, Antonio Tudisco, Salvatore Zammuto +7
Quantum error mitigation (QEM) provides a practical route for estimating reliable observables on noisy intermediate-scale quantum (NISQ) devices. Traditional QEM strategies, including zero-noise extrapolation (ZNE) and Clifford data regression (CDR), rely on noise scaling or global regression, and their performance is constrained by the exponential growth of the system degrees of freedom. We construct a graph-enhanced mitigation (GEM) framework, which incorporates physical information into the model representation. In this work, quantum circuits are encoded as attributed graphs. Hardware-level physical information is mapped to node and edge features: local noise parameters such as calibration parameters T1, T2, and readout errors are encoded at nodes, while coupling-related information such as two-qubit gate errors is encoded as edge features. Graph neural networks are used to model how errors propagate along the physical coupling structure and build up into non-local correlations. This allows the model to capture local interactions and part of the resulting non-local correlations across qubits. A dual-branch affine correction is applied to maintain consistency with physical constraints. Experiments on 10-qubit and 16-qubit random circuits executed on superconducting quantum processors show that GEM provides a level of accuracy comparable to CDR at small scales, while yielding lower mean absolute error and improved stability in zero-shot transfer to larger systems. Results of the traditional QEM strategy indicate that global regression methods remain effective in low-dimensional settings but become less reliable as system degrees of freedom grow. In contrast, GEM makes use of local physical structures to show better scalability and generalization, while preserving the overall error propagation patterns. This work provides a practical scalable approach to QEM for NISQ devices.
Fault-tolerant quantum computing (FTQC) relies on quantum error correction to suppress physical errors and preserve logical information at scale. In practice, however, performance is constrained not only by physical noise but also by the latency of classical decoders processing rapidly generated syndrome data. This challenge is exacerbated by hardware noise that is strong, heterogeneous, and nonstationary, as well as by the simulation-to-hardware distribution shift that can substantially degrade fixed neural decoders. We present QAdapt, a noise-adaptive neural pre-decoding framework for surface-code quantum error correction. QAdapt captures local spatiotemporal correlations in syndrome data, sequentially adapts to evolving noise conditions while mitigating catastrophic forgetting, and forwards the residual syndrome to a conventional global decoder. Across 110 synthetic out-of-distribution noise configurations for rotated surface-code memory circuits, QAdapt consistently reduces the logical error rate relative to the neural pre-decoding baseline. On Google's Willow benchmark data, without target-domain fine-tuning, it achieves reductions of up to 5.79 percent in logical error rate and 9.32 percent in backend decoding latency on the residual syndrome. These results demonstrate that QAdapt provides a practical and decoder-compatible approach to improving the robustness and backend decoding efficiency of quantum error correction under evolving hardware noise.