Joint Optimization of Memory and Computing Frequency for Energy-Efficient DNN Inference

Yunchu Han; Zhaojun Nan; Sheng Zhou; Zhisheng Niu

cs.AIAug 14, 2026

Joint Optimization of Memory and Computing Frequency for Energy-Efficient DNN Inference

Authors: Yunchu Han, Zhaojun Nan, Sheng Zhou, Zhisheng Niu

Organizations: Beijing National Research Center for Information Science and Technology Department of Electronic Engineering, Tsinghua University, Beijing 100084, China · School of Electronics and Internet of Things Chongqing Polytechnic University of Electronic Technology, Chongqing 401331, China

Abstract

Deep neural network (DNN) inference on mobile devices often incurs high latency and energy consumption due to limited computing and memory resources. To enable energy-efficient DNN inference, most existing studies focus on dynamic voltage and frequency scaling (DVFS) for adjusting the computing frequency, while the impact of memory frequency on the inference performance has been greatly overlooked. In this paper, we consider the impact of memory frequency and computing frequency on DNN inference time, and jointly optimize these two frequencies together with communication resources for energy-efficient DNN inference. Based on a realistic inference time model, we formulate an optimization problem to minimize the energy consumption of all mobile devices under the deadline constraint. For local inference, we derive a near-optimal closed-form solution via convex optimization, while an optimal closed-form solution for transmission power is obtained for edge inference with the given bandwidth. Furthermore, we propose a low-complexity heuristic algorithm to effectively solve the overall problem with polynomial time complexity. Simulation results based on measured data show that the proposed near-optimal solution for local inference can achieve optimal performance under strict deadline constraints, with a performance gap of up to 2.5% compared with the optimal solution. Meanwhile, our proposed algorithm significantly reduces the energy consumption of devices by up to 10.4% compared to other methods.

Figures & tables

Fig. 1: Impact of memory frequency scaling on DNN inference time and energy consumption for ResNet152 and VGG19 on Jetson TX1.

Fig. 2: Illustration of an edge intelligence system that jointly optimizes memory and computing frequencies, transmission power and bandwidth.

DNN Model	Mobile Device	$f_{n,\mathrm{mem}}$ (GHz)	$f_{n,\mathrm{com}}$ (GHz)	$a_{n}$	$b_{n}$	$c_{n}$	$d_{n}$	$\kappa_{n,\mathrm{mem}}$	$\kappa_{n,\mathrm{com}}$	$\sigma_{n}$
ResNet152	Jetson TX1	[0.102, 1.6]	[0.1536, 0.9984]	0.039	1.552	0.211	0.358	0.152	1.115	2.097
VGG19	Jetson TX1	[0.102, 1.6]	[0.1536, 0.9984]	0.110	1.296	0.099	0.629	0.152	1.115	2.097

TABLE I: Parameters of DNNs and Devices.

Fig. 3: Comparison for the local energy consumption of optimal and near-optimal solutions under different deadlines.

Fig. 4: Comparison for the memory frequency and computing frequency of optimal and near-optimal solutions under different deadlines.

Fig. 5: Energy consumption under various bandwidth resources and devices.

Efficient Neural Network Inference

Efficient neural network inference reduces the time, memory, and energy needed to run trained models across hardware and deployment settings.

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SparseDVFS: Sparse-Aware DVFS for Energy-Efficient Edge Inference

Ziyang Zhang, Zheshun Wu, Jie Liu, Luca Mottola

Politecnico di Milano, Milan, Italy · Harbin Institute of Technology, Shenzhen, China

Efficient Neural Network Inference Energy-Efficient ML Edge Inference

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Deploying deep neural networks (DNNs) on power-sensitive edge devices presents a formidable challenge. While Dynamic Voltage and Frequency Scaling (DVFS) is widely employed for energy optimization, traditional model-level scaling is often too coarse to capture intra-inference variations, whereas fine-grained operator-level scaling suffers from prohibitive performance degradation due to significant hardware switching latency. This paper presents SparseDVFS, a fine-grained, sparse-aware DVFS framework designed for energy-efficient edge inference. Our key insight is that operator sparsity is a primary metric for hardware frequency modulation. By distinguishing between compute-bound dense operators and memory-bound sparse operators, the system can apply specialized frequency triplets to maximize energy efficiency. To overcome switching overheads and component interference, SparseDVFS incorporates three key innovations: (1) an offline modeler that established a deterministic mapping between operator sparsity and optimal frequency triplets (CPU/GPU/EMC) via white-box timeline analysis; (2) a runtime graph partitioner that utilizes a greedy merging heuristic to aggregate operators into super-blocks, balancing scaling granularity and DVFS switching latency through a latency amortization constraint; and (3) a unified co-governor that employs a frequency unified scaling engine (FUSE) and a look-ahead instruction queue to eliminate antagonistic effects between independent controllers and hide hardware transition latencies. Extensive evaluations show that SparseDVFS achieves an average 78.17% energy efficiency gain over state-of-the-art solutions while maintaining a superior 14% cost-gain ratio.

Abstract

Efficient Neural Network Inference

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