cs.ARAug 18, 2026

ETHEREAL: A 25.6-μμs/inf. Low-latency Event-driven Graph-neural-network Processor for High-resolution Vision at the Edge

Authors: Adrian Kneip, Martin Lefebvre, Daniel Gehrig, Victoria Catalán Pastor, Davide Scaramuzza, Marian Verhelst, Charlotte Frenkel

Organizations: Microelectronics Department (EEMCS Faculty), Delft University of Technology, 2628 CD Delft, Netherlands · Department of Electrical Engineering, KU Leuven, 3000 Leuven, Belgium · University of Pennsylvania, PA 19104, Philadelphia, United States of America · Robotics and Perception Group, University of Zurich, Zurich, Switzerland

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Abstract

Dynamic vision sensors (DVS) are enticing candidates to reach the low-latency, sub-ms target of edge-vision applications, as they generate events with a μμs-level time resolution. However, using DVS front ends also calls for novel algorithm/hardware back ends capable of efficiently handling streams of sparse spatiotemporal events. While event-driven graph neural networks (EV-GNNs) have emerged as a solution on the algorithmic side that is both accurate and efficient, there is no dedicated hardware to date capable of efficiently supporting their mixed requirements of dense-regular compute operations and sparse-irregular memory accesses. We therefore introduce ETHEREAL, the first EV-GNN processor chip, capable of bridging this gap by means of a neighbor-parallel spline-convolution engine combined with a split-2D/3D memory hierarchy that introduces a novel spatiotemporal event-caching mechanism. Measurement results demonstrate a 25.6μμs latency and a 1.6μμJ energy per end-to-end event-wise inference on the state-of-the art DAGr-GNN workload and VGA-resolution (640x480 pixels) DSEC dataset.

Figures & tables

Fig. 1: (a) Frame- versus event-based edge-vision platforms, and gap in the state of the art. (b) Working principle of EV-GNNs.
Fig. 2: Illustration of graph convolution in modern EV-GNNs.
Fig. 3: Comparison between weight kernels for (a) a regular 2D convolution on a pixel grid, interpreted as a dense graph, and (b) a spline convolution with a 2D-spatial spline basis. Illustrated for kernel size K=3K=3 and spline degree D=1D=1 . ICIC and OCOC stand for input- and output-channel dimensions.
Fig. 4: State-of-the-art DAGr-type workload (based on [ 24 ] ) and its key properties: (a) high-resolution 3D spatiotemporal layers, (b) low-resolution 2D spatial-only layers, and (c) graph-convolution blocks, with optional CNN-feature concatenation.
Fig. 5: HW challenges stemming from the properties of state-of-the-art EV-GNN workloads on (a) the datapath and (b) the memory side.
Fig. 6: Overview of (a) the ETHEREAL chip and (b) the EV-GNN accelerator.
Fig. 7: (a) Three-phase decomposition of the spline-based MP operation, controlled by the accelerator’s spline generator. (b) Illustration of the accelerator, graph-convolution and message-passing dataflows.
Fig. 8: (a) High-level example of the spline-based message-passing operation in the EV-GNN accelerator. (b) Comparison of the total graph-convolution duration for different dataflows (at fixed memory bandwidth).
Fig. 9: Message-passing core’s operation during (a) linear-MAC and (b) spline-MAC phases of the spline-based graph-convolution.
Fig. 10: (a) Reconfigurable PE architecture, with (b) details of its configuration modes. (c) Mode-dependent adder tree, with bit alignment for multi-precision support.
Fig. 11: Architecture of a unified aggregation and node-update unit, highlighting its mixed INT/FP-to-INT rescaler with an error-correction logic for the accumulated FP-to-INT conversion residue.
Fig. 12: Principle and architecture of the 3D spatiotemporal cache with intertwined graph building, with illustration of (a) spatial mapping and impact on the neighbor-search process, (b) temporal evolution of the cache content and write-back conditions.
Fig. 13: Overall architecture of the 3D data memory subsystem and its direct-accessed external memory, under (a) neighbor-search read and (b) event write after write-back operation. The sequential order of accesses to external memory sections, when required, is pointed out.
Fig. 14: Performance benefits of the split 3D/2D memory hierarchy. (a) Hit rate for different 3D spatiotemporal cache lookup strategies, at fixed number of sets. (b) Comparison of spline-convolution latency with external-memory, single-SRAM and interleaved banked-SRAM 2D graph-data storage.
Fig. 15: 2D graph-data encoding and mapping to different memory banks.
Fig. 16: Qualitative illustration of system-level operation scheduling. (a) Baseline serial execution with CPU pooling and per-layer full reconfiguration, (b) serial execution with accelerated pooling and multi-layer precompiled configuration, (c) parallel graph-building and graph-processing execution, enabled by the decoupling between 2D and 3D memories.
Fig. 17: (a) Chip microphotograph, (b) measurement setup, and (c) algorithm-to-hardware deployment flow.
Fig. 18: (a) Voltage-frequency-power curve of the chip, measured on DAGr-GNN for 10 3 random events. (b) Power and area breakdowns.
Fig. 19: (a) Trade-off between latency per event, X/W operands precision and input channel ( ICIC ) depth for a single 2D layer ( OC=64OC=64 , 10 3 events, 0.95V). (b) Evaluation of 3D EMAs for different spatial radii rsr_{s} , with and without caching ( IC=16IC=16 and rt=10r_{t}=10 ms).
Fig. 20: System-level evaluation of DAGr-GNN based on chip measurements, showing the trade-off between classification/detection accuracy, latency and energy per event inference for different convolution types and operand bit precisions (10 3 events, 0.95V).
Fig. 21: (a) Evolution of the average latency and energy per event inference on DAGr-GNN with supply voltage, at the maximum operating frequency. (b) End-to-end latency breakdown per operation type across DAGr-GNN at 0.95V (10 3 events).
 GPUSNNEV-GNN
 Measured[ 17 ] (iii)[ 18 ] (iii)[ 31 ] (iii)[ 21 ][ 22 ][ 23 ]This Work (iii)
Year20262021202220242025202520262026
TechnologyA10014nm28nm40nmFPGAFPGAFPGA28nm
Supply [V]0.90.80.5-0.8–0.80.80.80.6-1
Freq. [MHz]–6013-11550-200200–20050-280
Total Memory–27MB138kB–780kB–500kB1.25MB
TABLE I: Comparison to the state of the art
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