cs.ARAug 23, 2026

Precision-Aware Variable Bit Processing Elements for Hardware-Efficient Systolic Array Designs

Authors: Dantu Nandini Devi, Madhav Rao

Organizations: Department of Electronics & Communication Engineering, IIIT-Bangalore, Karnataka, India

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Abstract

Systolic arrays (SAs) have emerged as prominent hardware accelerators for matrix operations in deep learning, while floating point number formats enable precision control across computational domains. This research investigates approximate computing techniques for floating point (FP) multipliers in Weight Stationary Systolic Arrays, focusing on IEEE 754 (FP32), TensorFloat-32 (TF32), and Brain Floating point (BF16) formats. By integrating partial product matrix (PPM) column truncation with positive and negative compressors in the FP multiplier architecture, we optimize the trade-off between computational efficiency and accuracy. NSGA-II optimization algorithm was employed to explore the vast design space for evolving FP multiplier designs, towards achieving substantial hardware improvements while maintaining acceptable output quality. Substantial hardware benefits were observed in the FP multiplier designs across various applications, while preserving output quality. The FP approximated Processing Elements designed in the SA was found to offer comparable CNN accuracy for models trained on MNIST, F-MNIST, and CIFAR-10 dataset. The FP approximated SA designs that fall in the top 10 CNN performance offered substantial hardware gains in the range of 66% to 92% footprint savings, 60% to 93% of power benefits with 21% to 54% improvement in the delay when compared with the corresponding exact implementations mentioned in the literature for running the model trained on CIFAR-10 dataset. The TF32 and BF16 approximated SA designs also achieved substantial gains while maintaining comparable CNN accuracy. Our findings confirm that targeted approximation in FP multiplier design significantly improves the efficiency of hardware accelerators for error-tolerant applications, establishing an effective approach to hardware resource optimization in contemporary computing architectures.

Figures & tables

Fig. 1: Schematic showing the input data flow and kernel weights in the Weight Stationary SA architecture.
Fig. 2: Schematic showing the three floating-point data formats with Sign, Exponent, and Mantissa bits.
Fig. 3: Example showing the difference between the reduction tree of (a) traditional multiplier and (b) proposed multiplier where the first 8 bits are truncated, 3 bits are approximated by employing Positive Column-Cum-Stage-wise Multiplier (PMCSI) compressor configuration. Note that the number of bits to be truncated and approximated is deduced from the Evolutionary Algorithm run.
Fig. 4: Example configuration evolved by NSGA-II for a 3×33\times 3 FP32-based SA, showing varied bit truncation, approximation strategies, and compressor configurations across individual PEs.
Fig. 5: Hardware Characteristics and SSIM for NSGA-II generated solutions for image processing applications.
SA ConfigDelay (ns)Area ( μ\mu m 2 )Power ( μ\mu W))Delay (ns)Area ( μ\mu m 2 )Power ( μ\mu W))Delay (ns)Area ( μ\mu m 2 )Power ( μ\mu W))
 FP32TF32BF16
3 ×\times 319.66849152.582728.51914.54814793.894239.25311.8069752.13168.419
5 ×\times 519.398148125.6722321.9914.76547699.082854.95811.80632202.72616.266
8 ×\times 819.753396673.2836333.0314.715130015.4042421.2211.80689811.2521774.04
TABLE I: Hardware Characteristics of benchmark SOTA based Exact SAs [ 51 , 28 ] .
TBITSABITSCOMBOSSIMDelay (ns)Area ( μ\mu m 2 )Power ( μ\mu W)
Averaging Filter : FP32
[38, 37, 35, 38, 39, 36, 39, 39, 36][0, 0, 0, 0, 1, 0, 0, 1, 2][-, -, -, -, 2, -, -, 3, 4]116.79418503.226334.844
[40, 42, 41, 39, 41, 40, 42, 39, 42][0, 0, 0, 0, 0, 0, 0, 0, 1][-, -, -, -, -, -, -, -, 4]0.997316.22616588.71294.539
[40, 43, 41, 42, 42, 42, 42, 41, 43][0, 0, 0, 1, 0, 0, 0, 0, 0][-, -, -, 6, -, -, -, -, -]0.993314.92415865.722272.112
[41, 46, 41, 40, 41, 44, 41, 44, 43][0, 0, 0, 1, 0, 0, 0, 0, 0][-, -, -, 6, -, -, -, -, -]0.986814.50713213.512219.505
[43, 46, 41, 38, 41, 47, 43, 43, 41][1, 0, 2, 3, 0, 0, 1, 2, 1][7, -, 8, 6, -, -, 7, 8, 8]0.982415.08113031.226212.709
TABLE II: Hardware Characteristics and Accuracy for NSGA-II generated solutions for top accuracies of image processing applications.
Fig. 6: Hardware Characteristics and SSIM for NSGA-II generated solutions for CNN applications.
TBITSABITSComboAccuracyDelay (ns)Area ( μ\mu m 2 )Power ( μ\mu W))
MNIST : FP32
[46, 43, 46, 43, 43, 46, 47, 44, 45][1, 3, 1, 3, 2, 0, 0, 2, 2][7, 8, 7, 8, 7, -, -, 7, 7]9913.4966081.10297.2133
[46, 46, 46, 42, 42, 47, 46, 43, 43][0, 1, 1, 1, 2, 0, 0, 0, 2][-, 6, 7, 6, 7, -, -, -, 7]989.5633595.78850.1269
[46, 45, 46, 42, 43, 47, 47, 44, 45][0, 1, 1, 3, 2, 0, 0, 1, 2][-, 8, 7, 7, 7, -, -, 8, 7]9713.1785931.64890.5751
[47, 44, 47, 42, 43, 46, 46, 44, 45][0, 2, 0, 3, 2, 1, 0, 2, 2][-, 6, -, 7, 7, 7, -, 7, 7]9613.555951.82691.9252
[46, 47, 46, 42, 43, 46, 46, 44, 44][0, 0, 1, 3, 2, 0, 0, 1, 2][-, -, 8, 7, 6, -, -, 7, 7]9510.8073556.45846.09
TABLE III: Hardware Characteristics and Accuracy for NSGA-II generated solutions for top accuracies for CNN application.
Fig. 7: Hardware Characteristics and SSIM for NSGA-II generated solutions for JPEG Compression application.
TbitsABITSComboSSIMDelay (ns)Area (um^2)Power (mW)
gray-scale Image : FP32
[30, 33, 31, 31, 33, 34, 30, 32, 31, 28, 31, 34, 30, 30, 29, 36,[1, 2, 3, 0, 1, 1, 1, 2, 1, 1, 1, 1, 1, 2, 2, 2,[2, 4, 3, -, 5, 2, 3, 3, 2, 2, 3, 4, 3, 3, 2, 3,0.999118.689208641.8884138.73
36, 32, 33, 33, 33, 32, 32, 27, 26, 31, 27, 33, 32, 31, 33, 28,1, 2, 1, 2, 0, 3, 4, 4, 3, 1, 2, 0, 2, 2, 2, 2,4, 1, 4, 3, -, 4, 2, 2, 2, 3, 3, -, 4, 3, 3, 3,
32, 32, 30, 32, 27, 30, 28, 28, 30, 24, 34, 31, 32, 27, 27, 32,2, 1, 3, 3, 2, 2, 2, 1, 3, 2, 1, 2, 0, 3, 0, 0,2, 4, 4, 4, 2, 3, 4, 3, 4, 2, 3, 3, -, 1, -, -,
25, 33, 32, 32, 27, 31, 34, 33, 28, 32, 32, 35, 30, 29, 33, 34]3, 1, 3, 0, 3, 3, 4, 0, 4, 1, 1, 1, 1, 1, 1, 3]3, 2, 2, -, 4, 4, 4, -, 2, 4, 3, 2, 3, 4, 2, 4]
[32, 31, 33, 29, 34, 31, 34, 31, 36, 31, 37, 34, 35, 32, 32, 36,[3, 2, 0, 1, 0, 2, 2, 2, 2, 1, 1, 1, 1, 3, 1, 1,[4, 1, -, 4, -, 5, 4, 1, 4, 4, 4, 4, 5, 6, 4, 3,0.996218.586184370.8323742.27
TABLE IV: Hardware Characteristics and SSIM for NSGA-II generated solutions for top accuracies in JPEG Compression.
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