Pipeline-Native Transformers: Co-Designing Model Architecture and CPU Inference for Bandwidth-Efficient Autoregressive Decode
Organizations: Independent Research Report
Abstract
Single-token autoregressive decode on CPUs is bound by memory bandwidth, not arithmetic: a modern CPU sustains roughly 1 TFLOP/s of compute but only about 50 GB/s from main memory, and each generated token must stream every active weight once. This report argues that the most effective response is to co-design the model architecture and the inference runtime together. It presents cflow, a CPU-first streaming engine, alongside a family of pipeline-native transformer architectures whose inter-layer dependency graphs are constructed to permit a vertical, stage-major execution schedule. cflow stores weights as L2-sized tiles in compute-consumption order, reads only the top-k experts of each mixture-of-experts layer, fuses projections, and executes a delay-aware schedule from per-model dependency parameters. Across five architectures trained on TinyStories, one (arch2_4_combined) achieves a 2.00x reduction in critical-path weight bandwidth (9.00 to 4.50 MB/token) within 0.24 perplexity of the best candidate, and the tile layout incurs 7.29x fewer L1-data read misses than a row-major baseline. On a 30.9-billion-parameter pipeline-native MoE, cflow decodes at 5.94 tokens/s (tok/s) on a 32-vCPU Ice Lake server, ahead of llama.cpp (4.75) and the vLLM CPU backend (1.65) on comparably sized dense models. Realizing the expert-delay window as asynchronous I/O overlap on a disk-resident expert tier yields a further net win of up to 1.68x, matching the overlap model within 1%. Measurement refutes one of the eight design claims and leaves a second inconclusive; both are reported in full, with the conditions under which they would hold.
Figures & tables
| # | Claim | Status / Headline Result |
|---|---|---|
| 1 | Conditional expert loading | Proven (structural): only top- expert tiles are read |
| 2 | Tile-streaming cache locality | Proven: 7.29 fewer L1-d misses (PMU, Xeon E5-2650, dense-down) |
| 3 | AVX2 Q4 kernels | Proven: implemented and validated against reference |
| 4 | Fused projections | Proven: QKV and gate-up from one activation cache load |
| 5 | Compute-order file layout | Proven by format construction |
| 6 | PREFETCHT0 prefetch | Refuted: PF=1 is 4% worse at 4.7 GB direct-I/O |
| Architecture | Style | Test PPL | ||||
|---|---|---|---|---|---|---|
| arch1_decoupled_streams | DecoupledStreams | 0 | 0 | 7.21 | 9.00 MB | 9.00 MB |
| arch2_4_combined | DelayedSum | 1 | 2 | 6.50 | 9.00 MB | 4.50 MB |
| arch2_4_sync † | DelayedSum | 1 | 0 | 6.52 | 9.00 MB | 4.50 MB |
| arch3_pipeline_registers | PipelineReg | 0 | 0 | 7.24 | 9.00 MB | 9.00 MB |
| arch4_async_experts | AsyncExperts | 0 | 2 | 6.26 | 9.00 MB | 9.00 MB |
| arch5_fixed_point | FixedPoint | 0 | 0 | 6.77 | 14.06 MB | 14.06 MB |
| Operation | Out In | Working Set / L1-d | Tiled Wins | Speedup |
|---|---|---|---|---|
| dense-down | 8192 32768 | 4 | yes | 1.28 |
| attn-proj | 8192 8192 | 1 | yes | 1.36 |
| dense-gateup | 32768 8192 | 1 | yes | 1.12 |
| expert-proj | 8192 8192 | 1 | yes | 1.20 |
| Operation | Tiled Misses | Naive Misses | Ratio (naive/tiled) | Working Set |
|---|---|---|---|---|
| dense-down | 2.64M | 19.3M | 7.29 | 4 L1-d |
| attn-proj | – | – | 6.75 | 1 L1-d |
| dense-gateup | – | – | 6.72 | 1 L1-d |
| expert-proj | – | – | 6.88 | 1 L1-d |
| # | Claim | Status and headline |
|---|---|---|
| 1 | Conditional expert loading | Proven (structural); reduction at Gemma scale |
| 2 | Tile-streaming cache locality | Proven; 7.29 fewer L1-d misses (PMU, Sandy Bridge) |
| 3 | AVX2 Q4 kernels | Proven; 124 tests pass; wall-clock win confirms throughput |
| 4 | Fused projections | Proven (structural); activation load savings |
| 5 | Compute-order layout | Proven (structural); sequential mmap invariant |
| 6 | PREFETCHT0 explicit prefetch | Refuted; at 64 MB, PF=1 4% worse at 4.7 GB |
| Configuration | tok/s | Speedup |
|---|---|---|
| Baseline (prefetch on, per-matmul chunk index) | 2.58 | 1.00 |
| prefetch disabled ( CFLOW_PREFETCH=0 ) | 4.96 | 1.92 |
| direct chunk indexing (no per-matmul allocation) | 5.94 | 2.30 |
| Engine | Model | Quant | tok/s |
|---|---|---|---|
| cflow | arch2_4_8k_16l (30.9B MoE, top-2/8) | Q4 | 5.94 |
| Ollama / llama.cpp | Qwen2.5-32B (dense) | Q4_K_M | 4.75 |
| vLLM CPU | Qwen2.5-32B-Instruct (dense) | GPTQ-Int4 | 1.65 |
| sync ms/tok | staged ms/tok | net | hidden | /layer | IO/layer | |
|---|---|---|---|---|---|---|
| 32 | 689 | 641 | 17% | 10.8 ms | 32.3 ms | |
| 16 | 739 | 644 | 19% | 13.6 ms | 32.6 ms | |
| 8 | 841 | 645 | 38% | 20.1 ms | 32.5 ms | |
| 4 | 1128 | 670 | 88% | 38.0 ms | 32.5 ms |
Efficient Transformer Inference
Efficient Transformer Inference studies methods and systems that reduce the latency, memory, and energy needed to run Transformer models.
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