LLM-Driven, Datasheet-Aware Automated Hardware Compatibility Verification for Early-Stage, Pre-Schematic Embedded System Design

Haotian Qiao; Robert P. Dick

cs.AIAug 25, 2026

LLM-Driven, Datasheet-Aware Automated Hardware Compatibility Verification for Early-Stage, Pre-Schematic Embedded System Design

Authors: Haotian Qiao, Robert P. Dick

Organizations: Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor, MI, USA

Abstract

We present an LLM-driven, datasheet-aware framework for early-stage hardware compatibility verification that identifies documentation-level interface incompatibilities based on hardware datasheets and high-level component connectivity descriptions. It does not require, and can therefore be used, before detailed schematic simulation and implementation. We view trustworthy LLM-assisted design automation not as directly generating answers from documents, but as transforming engineering information through traceable verification stages. Given hardware datasheets and high-level component connectivity descriptions, the framework constructs a design graph that captures device connectivity and shared interaction domains, retrieves only the engineering properties required by explicit, domain-oriented verification criteria , and generates deterministic scripts for compatibility evaluation. By decomposing compatibility analysis into modular stages and preserving intermediate results, the framework reduces context overhead, improves transparency and tractability, enables scaling, and avoids reliance on LLMs for numerical computation. Evaluated on seven embedded-system designs comprising 34 datasheets, our framework achieves 97.5% compatibility-verification accuracy and an 8.6 times reduction in input context size compared with ``upload-and-query'' workflows. These results demonstrate the feasibility of LLM-assisted, specification-based hardware compatibility verification at an early design stage, as well as the need for, and substantial benefits of, modular task decomposition, formalized verification criteria, and task-aware compact context construction.

Figures & tables

Fig. 1: The system pipeline of DEVICES. Verification criteria ((a), Section III-A ) guide property retrieval and verification script generation. Given a high-level component connectivity description, DEVICES constructs a design graph skeleton to represent system connectivity ((b), Section III-B ). For each netnode, relevant properties are then hierarchically retrieved from the hardware knowledge graph according to the required properties specified by the verification criteria ((c), Section III-C ). Finally, the retrieved properties, corresponding evaluation procedures, and deterministic compatibility rules are assembled into a task-aware context for each netnode, from which DEVICES generates a Python script for compatibility verification ((d), Section III-D ). Hardware knowledge graphs are constructed using our companion work.

Fig. 2: An example of the design graph with five devices in the system. Blue ellipses are netnodes and orange rectangles are device nodes. The design graph is generated from the high-level connectivity description: “The AP2114-3.3 through VIN pin is powered by the solar panel through JST2.0. The ESP32 through 3V3 pin, the BME280 through its VDD pin, and RRH46410 through its VDD pin are powered by the AP2114-3.3 through VOUT pin. The BME280 transmits data to the ESP32 via SPI. The RRH46410 transmits data to the ESP32 via I2C. All devices are physically in the same environment.”

Fig. 3: Compatibility verification accuracy of DEVICES and two baselines with and without verification criteria. Values inside the bars indicate the number of correctly evaluated constraints. Constraint evaluation is considered correct only if it uses the correct engineering properties, follows the required evaluation procedure, and reaches the correct compatibility conclusion; any violation is counted as failure. DEVICES achieves 97.5% accuracy, compared with 14.9% for the baseline without verification criteria and 62.7% for the baseline with verification criteria. These results demonstrate the importance of criteria and task-aware context refinement for early-stage, datasheet-aware compatibility verification.

Fig. 4: Input tokens of DEVICES and the two baselines with and without verification criteria. Input-token count measures the context size provided to the LLM. We use context size as an indicator of the amount of information the LLM must process, motivated by our evaluation results and prior studies showing that increasing context size degrades LLM performance, particularly when relevant information is surrounded by irrelevant content. For DEVICES, the reported value is the sum of input tokens across all netnode queries of each design; therefore, the context size of each individual query is substantially smaller than the reported total. The maximum context size is approximately 12.6k input tokens and the average context size per query is approximately 4.7k input tokens. The results also demonstrate the scalability of our modular context construction: as the design grows in complexity, DEVICES processes each netnode using a task-specific context rather than repeatedly inputting the complete datasheets to the LLM. Consequently, its per-query context remains substantially smaller than that of both one-shot baselines, allowing the LLM to focus on the relevant properties and verification instructions.

Electronic Design Automation

Electronic Design Automation uses algorithms and software to design, verify, optimize, and manufacture electronic circuits and systems.

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A Survey on LLM-Integrated Hardware Design Verification

Hao Zheng, Jaime Rafael Imperial, Bardia Nadimi, Xiangfei Kong

Bellini College of Cybersecurity, AI, and Computing, University of South Florida Tampa, FL, USA

LLM Agent Verification Formal Hardware Verification

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Large language models (LLMs) are increasingly being integrated into hardware verification to automate specification interpretation, verification-artifact generation, debugging, formal reasoning, and tool orchestration. This survey provides a systematic review of LLM-assisted hardware functional verification across SystemVerilog assertion generation, stimulus and testbench generation, bug localization and design repair, model checking and equivalence checking, SAT/SMT optimization, and emerging agentic verification workflows. We organize the literature by methodology, verification objective, tool interaction, benchmark, and evaluation criterion, and examine both inference-time techniques--including prompting, retrieval, structured reasoning, and agentic workflows--and training-time adaptation. Across these areas, a common pattern emerges: LLMs are most effective as semantic reasoning, search, and orchestration components embedded within verification-aware workflows, while simulators, formal engines, coverage tools, and solvers provide executable feedback and correctness evidence. However, tool acceptance alone does not establish verification correctness, since assertions, tests, repairs, or proofs may satisfy available checks without faithfully capturing the complete design intent. We therefore identify semantic alignment between specifications and verification evidence, scalable integration with deterministic tools, generalization to unseen designs, and rigorous evaluation of correctness, cost, robustness, and human effort as key challenges. Finally, we discuss emerging directions toward specification-centered, neuro-symbolic, and persistent agentic verification systems that combine LLM flexibility with independently checkable verification evidence.

Abstract

Electronic Design Automation

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