Mapping spiking neural networks (SNNs) onto neuromorphic many-core platforms is often formulated with graph partitioning and pairwise placement costs. That abstraction is convenient, but it does not match the physical communication event: one spike from a source neuron is delivered to a set of postsynaptic destinations, and routes to several destinations can share mesh links. We present M-HySMap, a route-aware, activity-weighted multicast hypergraph mapping framework. Each source neuron induces a directed hyperedge to its postsynaptic fanout, weighted by profiled activity. The mapper starts from strong activity-aware graph/QAP seeds and then optimizes distinct destination-core fanout, the union of deterministic mesh routes, and link congestion. The central algorithmic observation is locality: moving one neuron can change only its own source-rooted hyperedge and the hyperedges of its predecessors. This permits exact incremental gain evaluation while caching every unaffected route contribution. We expose this combinatorial structure in detail, derive a conservative placement lower bound, and describe a portfolio of partition and placement neighborhoods that preserves the best incumbent. Across a 115-job evidence suite on Potjans-inspired recurrent SNNs and mesh NoCs from 4 x 4 to 6 x 6, plus a 7 x 7 stress case, M-HySMap reduces routed multicast hops by 10.6-19.6% over Activity+QAP and 19.7-41.1% over Edge+QAP. Incremental updates accelerate refinement by 4.7-12.7x while matching full recomputation to numerical precision.
Figures & tables
Figure 1: Edge cut counts remote synapses independently. A multicast-aware view first collapses targets onto distinct destination cores; therefore equal edge cut need not imply equal network traffic.
Figure 2: Route-aware multicast cost uses the union of deterministic XY paths. Shared links are counted once per source spike. The union is the exact route set under the fixed routing policy; it is not claimed to be a minimum Steiner tree.
Figure 3: Search architecture. Strong activity-aware graph/QAP seeds are refined by route-aware neuron moves, multicast placement swaps, and alternating joint schedules. The portfolio returns the minimum-objective incumbent among its candidates.
Figure 4: Moving v affects hv and predecessor-rooted hyperedges. Unrelated source contributions are provably unchanged and remain cached.
Config
Cores
Seeds
Neurons
Synapses
0.0015, 4×4
16
20
79
238±12
0.002, 4×4
16
20
108
442±19
0.002, 5×5
25
20
108
442±19
0.002, 6×6
36
20
108
442±19
0.002, 7×7
49
5
108
440±6
0.003, 4×4
16
10
163
1028±36
Table 1: Benchmark configurations. The 7×7 case is a smaller stress run.
Config
Seeds
Edge+QAP
Activity+QAP
M-HySMap
vs Edge
vs Activity
0.0015, 4×4
20
1922±775
1409±643
1133±563
41.1%
19.6%
0.002, 4×4
20
8642±3618
7332±3341
5934±2677
31.3%
19.1%
0.002, 5×5
20
10389±4210
8535±3675
7309±3161
29.6%
14.4%
0.002, 6×6
20
13264±5563
10624±4990
9499±4404
28.4%
10.6%
0.002, 7×7
5
13819±4608
11079±3489
9603±2974
30.5%
13.3%
0.003, 4×4
10
113919±17494
102637±16546
84816±14631
25.5%
17.4%
Table 2: Main routed multicast hop results. Values are mean ± standard deviation. Improvements are hop reductions achieved by M-HySMap.
Figure 5: Normalized routed multicast hops. Activity+QAP is 1.0 in each configuration; M-HySMap improves the routed metric in all eight configurations.
Method
Norm.
Hops
Obj.
Max link
Edge+QAP
1.192
61290
65458
1986.1
Activity+QAP
1.000
55552
59391
1860.8
QAP-seeded M-HySMap
0.857
47653
50085
1523.7
M-HySMap
0.848
47527
49824
1479.3
Table 3: Compact ablation summary averaged over configurations.
Config
Full recompute (s)
Incremental (s)
Speedup
Avg. affected
Max error
0.0015, 4×4
0.438
0.061
7.2 ×
2.48
1.8×10−12
0.002, 4×4
1.044
0.113
9.2 ×
2.71
9.1×10−12
0.002, 5×5
1.676
0.356
4.7 ×
2.60
8.2×10−12
0.002, 6×6
2.462
0.431
5.7 ×
2.51
2.0×10−11
0.002, 7×7
1.747
0.351
5.0 ×
2.65
1.1×10−11
0.003, 4×4
11.844
0.933
12.7 ×
2.41
7.3×10−11
Table 4: Runtime benefit of exact incremental hyperedge updates.
Figure 6: Incremental update speedup. Labels also report the average number A of affected source hyperedges, illustrating why locality is valuable.
Many-core neuromorphic systems accelerate Spiking Neural Networks (SNNs), yet their packet-based spike communication can spend substantial traffic and energy repeatedly transmitting destination addresses. This overhead is amplified by the small payload of spike packets: in representative workloads, duplicate address transmissions account for up to 49% of the total traffic. This paper presents UniSpike, a hardware-software co-design that removes address redundancy by aggregating spikes destined for the same core into compact packets. UniSpike combines destination-centric spike scheduling, lightweight runtime packet assembly hardware, and destination-aware SNN partitioning. Across diverse SNN workloads, UniSpike reduces traffic by 1.93× on average, delivering 1.77× speedup and 1.50× energy efficiency improvement over state-of-the-art designs.
Energy-efficient neuromorphic computing at the edge requires simulation tools that can capture the non-ideal behavior of mixed-signal spiking neural network (SNN) hardware while supporting system-level design exploration. This work presents an open-source hardware-aware simulation framework for mixed-signal SNNs that enables comparative analysis across neuron, synapse and architecture choices. The framework supports multiple neuron models, including Leaky Integrate-and-Fire (LIF), Hodgkin-Huxley (HH) and Axon-Hillock (AH), together with non-volatile analog synapses based on floating-gate transistors and ReRAM devices. By incorporating device-level nonlinearities directly into PyTorch-based training and inference, the tool enables optimization of physical synaptic parameters rather than idealized abstract weights. The framework is evaluated on standard neuromorphic benchmarks, including N-MNIST, DVS Gesture and Spiking Heidelberg Digits (SHD). For each model dataset configuration, it reports classification accuracy together with hardware-oriented metrics such as silicon area, power consumption and quantization sensitivity. These capabilities enable cross-layer design space exploration and help identify neuron-synapse configurations that best satisfy application-specific constraints on accuracy, energy efficiency, area and hardware fidelity.
Efficient computation of shortest paths in weighted graphs is a fundamental problem with many applications. Neuromorphic hardware platforms promise massively parallel, efficient computation, changing parallelism tradeoffs. In this work, we introduce NEURO-MAPP (Neuromorphic-based Min-Add Parallel Propagation), a distributed shortest path algorithm designed to use the local computation and network communication available in neuromorphic systems. We provide an optimized implementation of the algorithm on the SpiNNaker 2 platform and evaluate its performance on a selection of synthetic and real-world graphs. These results are compared to Dijkstra's algorithm on a modern CPU. We find that the NEURO-MAPP implementation scales favorably in terms of runtime for many graph types while consuming less energy per shortest-path query than the CPU implementation in almost all cases. These findings highlight the potential of neuromorphic hardware featuring sparse, spike-based communication as a scalable and energy-efficient platform for computation in graph search and related tasks.
Oskar von Seeler, Elena C. Offenberg, Carlo Michaelis +4
Department of Neuro- and Sensory Physiology, University Medical Center Göttingen, Germany · Campus Institute Data Science, University of Göttingen, Germany · Third Institute of Physics – Biophysics, University of Göttingen, Germany +2