cs.ARAug 27, 2026

LLMs in Digital EDA: A perspective on shifting roles from Generation to Orchestration

Authors: Matthew Youngman, Cristian Sestito, Themis Prodromakis

Organizations: Centre for Electronics Frontiers, Institute for Integrated Micro and Nano Systems, School of Engineering, The University of Edinburgh, UK

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Abstract

Electronic design automation (EDA) has advanced engineering productivity through successive generations of tooling that progressively automate synthesis, optimisation, and verification. Large language models (LLMs) extend this trajectory by enabling direct translation from design intent to hardware implementations. In most of the EDA literature, LLM-based solutions are typically assisting siloed design stages or tasks, however this obscured the drivers by which capability emerges and systems scale. In this Perspective, we instead define three hierarchical roles that reveal how capability accumulates: a Generator that produces design artifacts in a single pass, an Agent that refines outputs through iterative tool feedback, and an Orchestrator that coordinates decisions across EDA-stages. Across published systems, this reveals a syntax trap in which models are trained to produce plausible code rather than physically correct hardware, compounded by fragmented tools and loss of design context that obscure how decisions affect later stages. Comparisons across the three roles show that current approaches struggle to scale to industrial designs, motivating a shift towards a standardised, physics-aware orchestrator that connects tools and agents across the EDA flow for more reliable and accessible hardware design.

Figures & tables

Figure 1: Overview of LLMs’ current integration within the digital EDA design flow. Shows a, technology abstraction levels, b, the sequential digital design stages, and c, the roles LLMs are taking at each step. Identifies “syntax traps” where a lack of physics awareness leads to less effective LLM application.
Figure 2: Trends in LLM maturity and the landscape of current research. a, Taxonomy of field across 46 papers, connecting each paper’s EDA function, LLM method stack and LLM role. The progression of LLM capabilities across three axes: b, autonomy (degree of agentic workflow control), c, explainability (decision provenance), and d, evaluation focus (target design challenge ), with annotated trend lines of gradients normalized to axis scale; points sharing the same rank are offset for clarity only. Survey results are in Supplementary Table 1 and figure is interactive at https://mattycode101.github.io/LLMs_in_Digital_EDA_Perspective/ .
Figure 3: Nested LLM architecture framework and multi-axis productivity evaluation . a, Orchestrator Tier: Collaborative interface between Human, LLM Orchestrator & Provenance Database. b, Agent Tier: Numerous stateless agents/generators have specifications provided by Orchestrator and execute these in custom pipeline. c, Tool Tier: access to EDA tools for verification of artifacts and design development. d, e, Five-axis productivity comparisons for Spec-to-RTL generation across (d) modular-level ( ≤\leq 150 lines of code) and (e) system-level ( >> 200 lines of code) design complexities. Generator, Agent, and Orchestrator LLM architectures are evaluated against human Engineer baselines; see Supplementary Table 2 for plotted results, methodology, and sources.
Figure 4: Digital design scenarios of Orchestrator System capabilities radiate from a) The Smart Lab, a central environment for the LLM orchestrator to coordinate physical or simulated experimentation. This environment enables: b) Workflow Automation, support across the EDA flow in near future, shifting engineers towards intent setting and review c) PPA-driven DSE, utilizing agentic search for multi-objective optimization; and d) Automated Security Probing, integrating hardware defensive checks with awareness of LLM adversarial misuse.
NicknameRef.DateDesign FunctionMethod StackRoleAutonomyExplainabilityEval.
Chip-Chat[ 6 ]May 2023RTL Gen.Task Struc.GeneratorHuman-in-the-loopChain-of-Thought (CoT)Syntactic Correctness
ChipGPT[ 27 ]May 2023RTL Gen.RAG & ICL; Task Struc.; Feedback Looped; DSEAgentHuman-in-the-loopBlack Box GenerationPPA Metrics
VeriGen[ 12 ]Jul 2023RTL Gen.Pre-training & SFTGeneratorHuman-guidedBlack Box GenerationFunctional Correctness
RTLLM v1[ 38 ]Aug 2023Dataset Constr.Eval. Suite; Task Struc.GeneratorHuman-guidedChain-of-Thought (CoT)Functional Correctness
ChatEDA[ 13 ]Aug 2023RTL Gen.; EDA ScriptingTask Struc.; Pre-training & SFT; Data Aug.AgentHuman-in-the-loopChain-of-Thought (CoT)Functional Correctness
GPT4AIGChip[ 28 ]Sep 2023RTL Gen.RAG & ICL; Task Struc.; Feedback LoopedAgentHuman-in-the-loopPipeline Stage CollectionFunctional Correctness
Table 1: Taxonomy of LLM-for-EDA papers (2023–2026), The table records a manual coding of each system against a fixed schema of categorical (function, method, role) and ordinal (autonomy, explainability, evaluation focus) dimensions, each dimension having a closed set of defined levels; every paper was assigned its single best-fitting level, ordinal dimensions ranked 1…N by increasing capability, and dated by first public release. The growth rates were then obtained by least-squares regression of ordinal level against date, normalised to the axis span (N) and reported as percent of full scale per year (autonomy 8.8%, explainability 5.8%, evaluation focus 6.9%). Task abbreviations : RTL Gen. = RTL Generation; EDA Scripting = EDA Script Generation; Sim. & Verif. = Simulation & Verification; Dataset Constr. = Dataset Construction. Method abbreviations : RAG & ICL = Retrieval Augmented Generation / In-Context Learning; Pre-training & SFT = (Continued) Pre-training & Supervised Fine-Tuning; Task Struc. = Task Structuring; Feedback Looped = Iterative Feedback Loop; LLM-MA = LLM Multi-Agent System; DSE = Design Space Exploration / Tree Search; RL = Reinforcement Learning; Data Aug. = Data Augmentation; Eval. Suite = Benchmarking / Evaluation Suite. Column headers : Ref. = Reference; Eval. = Evaluation Focus.
ChartAxisTierVal.UnitPapersModel(s)Benchmark(s)Notes
Modular (Component-Level, ≤\leq 150 LOC)
ModularCorrectnessHuman95%Estimate——Assumed marginal human error rate
ModularCorrectnessGenerator59.8%[ 39 ] , [ 46 ] , [ 11 ] , [ 19 ] , [ 51 ] , [ 37 ]GPT-4, GPT-4oVerilogEval [ 39 ] , RTLLM [ 38 ]Median of 6 pass@ kk
ModularCorrectnessAgent72.0%[ 19 ] , [ 11 ] , [ 37 ] , [ 46 ]GPT-4, GPT-4oVerilogEval [ 39 ] , RTLLM [ 38 ] , RealBench [ 37 ]Median of 5 pass@ kk
ModularCorrectnessOrchestrator62.9%[ 51 ]GPT-4-turboAutoSilicon [ 51 ]Single study
ModularPPAHuman1.00×\timesDefinitional——Reference denominator
Table 2: The table covers specification-to-RTL only (the most measurable, best-evidenced stage), split by benchmark module size into component ( ≤\leq 150 lines of code ) and system ( >200 lines of code ) tiers. Each value is a multi-source central estimate, pooled across cited studies to hold the task fixed and limit conflation of model, benchmark, and metric, with per-cell provenance in the Notes column; correctness is the median reported func@1 or pass@1 (when available), PPA the median geometric mean of normalised area-power ratios against human baselines, verification integrity the ratio of functionally-validated ( form@k ) to synactically correct ( synt@k ) designs, time and cost measure the reported end-to-end automated runtime ( seconds ) and cumulative API expenditure ($) per design respectively. Unreported cells are estimated from tier and trend, and flagged as projected. Human baselines are fixed by definition where used as references (correctness and verification integrity = 100%, PPA = 1.00×), and human time and cost are derived from an engineer estimated design effort and hourly rate respectively.
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